To provide a variation adjustment circuit that has a simple circuit configuration and achieves size reduction.

The variation adjustment circuit 1 is provided with a delay circuit 3 for variation adjustment constituted of a plurality of unit delay circuits 27, flip-flops 10-17 for outputting signals C to I in turn for each clock of a clock signal CLK when a signal A is inputted to the delay circuit 3 for variation adjustment, flip-flops 18-25 for outputting one of selection signals Q0-Q7 when a signal outputted from the corresponding flip-flop is inputted after a signal B is outputted from the delay circuit 3 for variation adjustment, and a control circuit 26 that operates an exclusive OR of each signal outputted from two flip-flops which output consecutive signals, of the flip-flops 18-25 and adjusts a delay time of a delay circuit 2 on the basis of the calculation result.