Title:
VECTOR ABSOLUTE VALUE ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JP3522457
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an analog vector absolute value arithmetic circuit having a small amount of hardware with high accuracy.
SOLUTION: A signal voltage corresponding to a component I (a real number part) and a component Q (an imaginary number part) is inputted respectively from terminals 11 and 12, and converted into each absolute value signal in a 1st absolute value circuit 13 and a 2nd absolute value circuit 14. The absolute value of the component I and the absolute value of the component Q are compared with each other at a comparing circuit 20, and multiplexers 21 and 22 are controlled according to the comparison result, so that the larger absolute value signal is outputted to the input capacitance 23 of a neuro-computing circuit and the smaller absolute value signal is outputted to an input capacitance 24. The capacitance ratio of the feedback capacitance 26 to the input capacitance 23 to the input capacitance 24 of the neuro-computing circuit is defined as 11:10:5, and an absolute value having a complex number which is computed by the approximate expression (10/11)Max(&verbar I&verbar , &verbar Q&verbar )+(5/11)Min(&verbar I&verbar , &verbar Q&verbar ) is outputted from an output terminal 27.
Inventors:
Shu, Nagaaki
Kotobuki, Kokuriyou
Suzuki, Kunihiko
Motohashi, Kazunori
Yamamoto, Makoto
Takatori, Sunao
Kotobuki, Kokuriyou
Suzuki, Kunihiko
Motohashi, Kazunori
Yamamoto, Makoto
Takatori, Sunao
Application Number:
JP22940296A
Publication Date:
April 26, 2004
Filing Date:
August 13, 1996
Export Citation:
Assignee:
YOZAN:KK
International Classes:
G06G7/22; G06G7/25; (IPC1-7): G06G7/25
Attorney, Agent or Firm:
高橋 英生 （外１名）
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