WORKING/CHANGE VERIFICATION METHOD IN LAYOUT PROCESSING, VERIFICATION DEVICE AND PROGRAM

Title:

WORKING/CHANGE VERIFICATION METHOD IN LAYOUT PROCESSING, VERIFICATION DEVICE AND PROGRAM

Document Type and Number:

Japanese Patent JP2008204340

Kind Code:

A

Abstract:

To achieve a verification device for easily determining whether or not the change of a netlist satisfies timing constraints and design constraints in the layout processing of a semiconductor device.

This working/change verification device 63 in working and changing an input netlist 10 including the logic information of a semiconductor device in layout processing is provided with a confirmation processing part for confirming that timing constraint conditions and design constraint conditions 64 included in the logical information are satisfied even after working and change; and an output part for, when those constraint conditions are not satisfied, outputting the information of the unsatisfied portion.

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Inventors:

TSUCHIYA ATSUSHI

Application Number:

JP2007042137A

Publication Date:

September 04, 2008

Filing Date:

February 22, 2007

Export Citation:

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Assignee:

FUJITSU LTD

International Classes:

G06F17/50; H01L21/82

Attorney, Agent or Firm:

Atsushi Aoki
Jun Tsuruta
Kurachi Yasuyuki

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