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Title:
VFO CIRCUIT
Document Type and Number:
Japanese Patent JPS5558634
Kind Code:
A
Abstract:

PURPOSE: To extend a range where input signals can be led in, by switching the maximum detection error quantity of a saw tooth wave phase comparator to the double of a normal leading-in state at an input signal leading-in time.

CONSTITUTION: Input signal pulses (period T0) are inputted to one shoot circuits SS1 and SS2 having set pulse width T0/4 and T0/2 respectively. Only at an input signal leading-in time, switching circuit 3 transfers the output of SS2 to edge detection circuit 4 by leading-in signals, and signals (period To) obtained by dividing output signals (period TO/2) of VCO9 into two by frequency divider circuit 6 are inputted to edge detector 6 by switching circuit 5, and outputs of edge detectors 7 and 4 are inputted to flip flop 8 and pass through inverter circuits 10 and 11 and NOR circuits 12 and 13, thereby outputting phase advance error and phase delay error.This output is converted to a voltage or a current by phase converter 14 and passes through low-pass filter 15 and VCO9,thereby feeding back the voltage or the current above to the input.


Inventors:
SHIRAISHI KAZUHISA
Application Number:
JP13055778A
Publication Date:
May 01, 1980
Filing Date:
October 25, 1978
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11B20/14; H03L7/10; (IPC1-7): G11B5/09
Domestic Patent References:
JPS4999466A1974-09-19
JPS52132759A1977-11-07



 
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