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Title:
VIDEO SIGNAL PROCESSING CIRCUIT
Document Type and Number:
Japanese Patent JPH06245195
Kind Code:
A
Abstract:

PURPOSE: To provide a video signal processing circuit capable of adding correction nonlinear in a horizontal direction to video signals by clocks which are not frequency modulated.

CONSTITUTION: The video signals are written in line memories 3 and 4, a data buffer 21 holds two pieces of adjacent pixel data and a mixer 22 mixes the two pieces of the pixel data by an optional interpolation coefficient and outputs interpolation data. A ROM or RAM 23 outputs geometrical distance data between the respective picture elements of a horizontal period in the video signals as an increment. The cyclic adder 24 for the number of finite bits adds the inputted increment and the output. The read of the line memories 3 and 4 and the updating of the pixel data of the data buffer 21 are controlled by the most significant bit of the data outputted from the adder 24 and the interpolation coefficient of the mixer 22 is controlled by the lower-order bits excluding the most significant bit.


Inventors:
SAWADA SHIGERU
Application Number:
JP4859393A
Publication Date:
September 02, 1994
Filing Date:
February 15, 1993
Export Citation:
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Assignee:
VICTOR COMPANY OF JAPAN
International Classes:
H04N5/93; H04N5/46; H04N7/01; (IPC1-7): H04N7/01; H04N5/93