To enable a high-speed writing/reading in/from a field memory and also to optimize the memory capacity by a time compression device to compress a video signal into one third.

Samples of 910 pieces of video signals per one line are delayed by two clocks by a two-clock delay circuit 31 and by one clock (CK) by a one-clock delay circuit 32, when three successive samples are fetched in parallel into a latch 33. The samples are fetched into a one-clock delay circuit 34 at the timing of WMCK (writing clock), and are fetched into VRAMs 35-37 at the following WMCK. WMCK divides CK to 1/3 and is also formed so that the duty changes during a horizontal blanking period. Reading from VRAMs 35-37 is performed by a clock with a frequency three time as many as WMC.