Title:
VITERBI DECODING CIRCUIT
Document Type and Number:
Japanese Patent JP2002009636
Kind Code:
A
Abstract:
To provide a Viterbi decoding circuit that can prevent overflow of path metrics, without increasing the latency of the circuit.
An ACS circuit is provided with a subtractor circuit, an alarm signal is given to the subtractor circuit when a main comparator circuit detects that each path metric is a predetermined threshold or larger, and each ACS circuit subtracts a predetermined decreased value from the path metric, on the basis of the alarm signal to conduct subtractor processing in the clock of the same ACS processing.
Inventors:
ONO SHIGERU
MATSUZAKI HARUHIKO
MATSUZAKI HARUHIKO
Application Number:
JP2000189994A
Publication Date:
January 11, 2002
Filing Date:
June 23, 2000
Export Citation:
Assignee:
NEW JAPAN RADIO CO LTD
International Classes:
G06F11/10; H03M13/41; (IPC1-7): H03M13/41; G06F11/10
Attorney, Agent or Firm:
Nagao Tsuneaki
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