PURPOSE: To reduce a generating offset voltage by compensating the effect of a base current of a 3rd transistor(TR) being a component of an output buffer with a base current of a 4th TR connected in series between the collector of the 3rd TR and a power supply.

CONSTITUTION: A differential amplifier circuit comprising NPN TRs Q1,Q2 uses a current mirror circuit 3 as an active load and the output is fed back to a base of the TR Q2 via an NPN TR Q3. Thus, a signal inputted from an input terminal 1 is outputted from an output terminal 2 without a change in the voltage. Moreover, an NPN TR Q4 is in cascade connection between a collector of the output buffer TR Q3 and a power supply Vcc and a base of the TR Q4 is connected to a collector of the NPN TR Q1. Since the effect of a base current of the TR Q3 is compensated by a collector current of the TR Q1 and a base current of the TR Q4, the collector current of the TRs Q1,Q2 is made equal and an offset voltage caused between terminals 1, 2 is decreased.