To shorten the offset cancel preparation period.
The drains of the MOS transistors M8 and M9 of a differential pair input circuit 16 are connected severally to the first and second current ends of the current mirror circuit 14 of a differential amplifying circuit 11. Reference potential Vref is applied to the gate of the MOS transistor M9. A switch SW1 is connected between the gates of the differential pair MOS transistors M1 and M2 of the differential amplifying circuit 11. A switch SW2 is connected between the output end VO of an output buffer circuit 12 and the gate of the MOS transistor M1. A switch S3 is connected between the very output end VO and the gate of the MOS transistor M8. In the offset cancel preparation period, the switches SW1 and SW3 are turned on, and the switch SW2 is turned off. Next, the switches SW1-SW3 are reversely turned on and off, and potential where the offset is cancelled is outputted.
UTO SHINYA
TSUCHIYA CHIKARA
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