Title:
電圧減算回路及びそれを用いた強度検波回路
Document Type and Number:
Japanese Patent JP4088247
Kind Code:
B2
Abstract:
A voltage subtracting circuit includes a conversion circuit, a holding circuit, and a differential voltage generator. The conversion circuit converts a first voltage input during a first period into a first current proportional to the first voltage. The conversion circuit further converts a second voltage input during a second period following the first period into a second current proportional to the second voltage. The holding circuit holds the first current during the first period as a third voltage. The holding circuit further outputs the first current during the second period on the basis of the third voltage. The differential voltage generator outputs a differential voltage between the second voltage and the first voltage during the second period on the basis of the second current output by the conversion circuit and the first current output by the holding circuit.
Inventors:
Toru Tanzawa
Application Number:
JP2003431450A
Publication Date:
May 21, 2008
Filing Date:
December 25, 2003
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03F3/34; H03F3/45; G06G7/14; G06G7/24; H03G3/30; H04B1/26
Domestic Patent References:
| JP8265115A | ||||
| JP58215108A | ||||
| JP5022159A | ||||
| JP1102798A | ||||
| JP4170808A |
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto