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Patent Searching and Data


Title:
WAFER LEVEL PACKAGING CAP AND METHOD FOR MANUFACTURING THE SAME
Document Type and Number:
Japanese Patent JP2006216963
Kind Code:
A
Abstract:

To provide a wafer level packaging cap and its manufacturing method for preventing the damage of the connection part of a connection bar and a cap substrate at the time of testing temperature-proof performance, and for easily machining the connection hole of a wafer having a high cross-section rate.

This wafer level packaging cap is provided with: a cap wafer formed with a cavity part with a predetermined capacity providing a space where an element is housed at its bottom face, and integrated with an element wafer; a plurality of metal lines formed on the bottom face of the cap wafer corresponding to each of a plurality of element pads formed so as to be electrically connected to elements on the element wafer; a plurality of buffering parts with which the plurality of metal lines are electrically brought into contact, and composed of buffering wafers forming a plurality of grooves and metal filled in the plurality of grooves; a plurality of connection bars electrically connected respectively to the plurality of buffering parts, and formed so as to be put from the upper side of the buffering parts penetrating the cap wafer; and a plurality of cap pads formed on the upper face of the cap wafer, and electrically connected to the upper ends of the plurality of connection bars, respectively.


Inventors:
LEE MOON-CHUL
KIM WOON-BAE
BACK KAE-DONG
WANG QIAN
HWANG JUN-SIK
JUNG KYU-DONG
Application Number:
JP2006028001A
Publication Date:
August 17, 2006
Filing Date:
February 06, 2006
Export Citation:
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Assignee:
SAMSUNG ELECTRONICS CO LTD
International Classes:
H01L23/02; H01L23/06
Attorney, Agent or Firm:
Yukio Ono
Tomoko Inazumi