Title:
WAIT ARBITER
Document Type and Number:
Japanese Patent JP3292308
Kind Code:
B2
Abstract:
PURPOSE: To provide a wait arbiter which can contribute to reduction of the communication processing time of data signals by providing a comparator and a control circuit which discontinues the production of the wait signals in accordance with the affirmative deciding signal of the comparator.
CONSTITUTION: The range information is shown by the head address value and the end address value and these address values are stored in the registers 52A and 52B respectively. A comparator 53 compares the address value shown by the address signal applied on an address bus with the head address value of the register 52A. When the former address value is larger than the latter address value, a signal of a level H is outputted. Meanwhile a comparator 54 compares the address value shown by the address signal on the address bus with the end address value of a second register. Then a signal of a level H is outputted when the former address value is smaller than the latter value. A gate circuit 56 generates a wait start signal of a level H when all output signal levels of the gate circuits 55 are equalt to '1'.
Inventors:
Fumio Ikeshima
Application Number:
JP3188492A
Publication Date:
June 17, 2002
Filing Date:
February 19, 1992
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
G06F13/14; (IPC1-7): G06F13/14
Domestic Patent References:
| JP3201156A | ||||
| JP63249253A |
Attorney, Agent or Firm:
Yoshikazu Tani (1 person outside)