Title:
WAIT CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPH04241056
Kind Code:
A
Abstract:
PURPOSE: To improve the throughput of the whole system at the time of DMA transfer by inserting proper weight numbers by devices at the time of DMA operation between I/O devices which differ in access speed.
CONSTITUTION: The wait numbers by the I/O devices are set in a register 21 in advance by using a CPU. In the DMA, a decoder 22 detects I/O device in operation and reads the wait numbers corresponding to the detected devices out of the register 21. A wait signal generation part 23 generates wait signals according to the read wait numbers, thus generating optimum wait signals for the individual devices.
Inventors:
TAMURA HIROYUKI
HIRAI YOSHITOKU
HIRAI YOSHITOKU
Application Number:
JP2392691A
Publication Date:
August 28, 1992
Filing Date:
January 24, 1991
Export Citation:
Assignee:
NEC CORP
NEC SHIZUOKA LTD
NEC SHIZUOKA LTD
International Classes:
G06F13/28; (IPC1-7): G06F13/28
Attorney, Agent or Firm:
Nobu Yanagikawa