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Title:
重み符号固定学習装置
Document Type and Number:
Japanese Patent JP6901163
Kind Code:
B2
Abstract:
A neural network circuit is provided with which it is possible to significantly reduce the area occupied by the connection unit of a full connection (FC)-type neural network circuit. An analog-type neural network circuit constitute a learning apparatus having a self-learning function and corresponding to a brain function, wherein the neural network comprises: a plurality (n) of input-side neurons; a plurality (m, and including cases when n=m) of output-side neurons; (n×m) connection units each connecting one input-side neuron and one output-side neuron; and a self-learning control unit, the (n×m) connection units being constituted from connection units corresponding to only the positive weighting function as a brain function, and connection units corresponding to only the negative weighting function as the brain function.

Inventors:
Tetsuya Asai
Application Number:
JP2019505784A
Publication Date:
July 14, 2021
Filing Date:
February 13, 2018
Export Citation:
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Assignee:
National University Corporation Hokkaido University
International Classes:
G06N3/063; G06G7/14; G06G7/16
Domestic Patent References:
JP8505982A
JP5181993A
Other References:
YAKOPCIC, Chris et al.,Memristor Crossbar Deep Network Implementation Based on Convolutional Neural Network,2016 International Joint Conference on Neural Networks,IEEE,2016年11月03日,pp.963-970,https://ieeexplore.ieee.org/document/7727302/,
HASAN, Raqibul et al.,Enabling Back Propagation Training of Memristor Crossbar Neuromorphic Processors,2014 International Joint Conference on Neural Networks,IEEE,2014年09月04日,pp.21-28,https://ieeexplore.ieee.org/document/6889893/,
Attorney, Agent or Firm:
Patent Business Corporation Intect International Patent Office
Kazuyuki Oku
Mikawa Corporation



 
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