To suppress variation in the capacitive load of a preceding circuit by connecting a variable additional capacitive load in parallel with capacitive coupling and controlling the additional capacitive load in accordance with the load state of the capacitive coupling.
A sample and hold circuit SH is connected to the input of an weighted adding circuit MUL and an additional capacitive load VL parallel with capacitive coupling is connected to the node N of the circuit SH. The load VL connects the one-terminals of plural capacitors C21, C22 to the node N respectively through multiplexers MUX21, MUX22 and connects the other terminals of the capacitors C21, C22 to reference voltage VREF. The input terminal of an inverted amplifier circuit 12 is always held at the reference voltage VREF and voltage equal to the output side voltage of the capacitive coupling is impressed to the capacitors C21, C22. At the time, the total loads of a capacitive load L1 and a capacitive load L2 is impressed to the node N. Consequently the variation of all the loads can be suppressed and all the loads are uniformed.
SHU NAGAAKI
CHIN TAKASHI
