WIRING BOARD, SEMICONDUCTOR DEVICE USING THE SAME, AND ITS MANUFACTURING METHOD

Title:

WIRING BOARD, SEMICONDUCTOR DEVICE USING THE SAME, AND ITS MANUFACTURING METHOD

Document Type and Number:

Japanese Patent JP2007234999

Kind Code:

A

Abstract:

To prevent the short-circuit of the connection part of a wiring board on which a semiconductor chip is wire bonded.

A wiring board such as an EPC 5 on whose surface a plurality of wiring patterns 8 are formed is characterized by forming an insulating cover ray 12 covering the section of lands 9 of the wiring patterns 8, and structured so that the short-circuit of those lands 9 can be prevented from occurring. In the case of wire-bonding a semiconductor chip 3, the connection of a wire 13 is carried out through the cover ray at the connection part of the wire 13 so that its short-circuit with the land 9 which is not the object of connection or a wiring part 11 following this land can be prevented from occurring.

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Inventors:

OHIRO MASAHIKO
NANO MASANORI

Application Number:

JP2006057039A

Publication Date:

September 13, 2007

Filing Date:

March 03, 2006

Export Citation:

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Assignee:

MATSUSHITA ELECTRIC IND CO LTD

International Classes:

H01L21/60; H01L23/12

Attorney, Agent or Firm:

Takao Itagaki
Yoshihiro Morimoto
Toshiji Sasahara
Yohei Harada

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