Title:
不揮発性記憶装置の書込み方法
Document Type and Number:
Japanese Patent JP4084922
Kind Code:
B2
Abstract:
There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.
Inventors:
Kenjun Takase
Kubo Nozomi
Mitsutaro Kanemitsu
Atsushi Nozoe
Keiichi Yoshida
Kurata Hideaki
Kubo Nozomi
Mitsutaro Kanemitsu
Atsushi Nozoe
Keiichi Yoshida
Kurata Hideaki
Application Number:
JP2000391229A
Publication Date:
April 30, 2008
Filing Date:
December 22, 2000
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C16/02; G11C11/56; G11C16/04; G11C16/06; G11C16/10; G11C16/12
Domestic Patent References:
| JP2001085540A | ||||
| JP2000293994A | ||||
| JP10275484A | ||||
| JP6349289A | ||||
| JP11191298A | ||||
| JP2001101879A |
Attorney, Agent or Firm:
Shizuyo Tamamura