Title:
A circuit model generation method, a device, and a program
Document Type and Number:
Japanese Patent JP6010971
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a method, a device and the like, capable of automatically generating a circuit model for an analog circuit.SOLUTION: A reception unit 11 of a circuit model generation device 1 receives a circuit simulation waveform 2. An output/transition time acquisition unit 13 acquires an output value (DC level) for each of a plurality of input values to the simulation waveform 2, and a transition time spent from input until output is stable. A mathematical formula model construction unit 15 generates a mathematical formula model representative of a relation between input and output from a set of each input value and an acquired output value, and sets transition time information for each change of input to the mathematical formula model on the basis of the acquired transition time. A circuit model generation unit 17 generates a circuit model 3 in which the mathematical formula model is described in an analog HDL.
Inventors:
Hayao Gokita
Application Number:
JP2012079707A
Publication Date:
October 19, 2016
Filing Date:
March 30, 2012
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F17/50
Domestic Patent References:
| JP2000250952A | ||||
| JP2005242398A | ||||
| JP9006814A | ||||
| JP2003316845A | ||||
| JP2000331054A | ||||
| JP10222553A |
Foreign References:
| US20070046676 | ||||
| WO2013132642A1 |
Attorney, Agent or Firm:
Keiko Shigehisa
Akihiko Watanabe
Akihiko Watanabe
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