Title:
CLOCK DATA RECOVERY CIRCUIT AND SIGNAL TRANSMISSION SYSTEM
Document Type and Number:
Japanese Patent JP2016208398
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a clock data recovery circuit which does not have any restriction in frequencies of data by performing control in such a manner that frequency pull-in can be implemented even in the case where a large frequency difference is present, and a signal transmission system.SOLUTION: The clock data recovery circuit comprises: a voltage controlled oscillator 11 which controls an oscillation frequency by a control voltage; a programmable divider 12 that is connected to the voltage controlled oscillator; a phase frequency comparator 13 that is connected to the programmable divider; a frequency comparator 14 that is connected to the voltage controlled oscillator; a phase comparator 15 that is connected to the voltage controlled oscillator; selection parts 17a and 17b that are connected to the phase frequency comparator and the frequency comparator; a charge pump FD 18 that is connected to the selection parts; a charge pump PD 19 that is connected to the phase comparator; and a loop filter 20 that is connected to both the charge pumps and the voltage controlled oscillator.SELECTED DRAWING: Figure 1
Inventors:
MIYASHITA KIYOSHI
Application Number:
JP2015090312A
Publication Date:
December 08, 2016
Filing Date:
April 27, 2015
Export Citation:
Assignee:
ASAHI KASEI DENSHI KK
International Classes:
H04L7/033
Attorney, Agent or Firm:
Tetsuya Mori
Hide Tanaka Tetsu
Hide Tanaka Tetsu
Previous Patent: 車両用通信システム及び携帯機
Next Patent: A terminal unit, an information service system, and a program
Next Patent: A terminal unit, an information service system, and a program