Title:
The control method of a semiconductor memory device and a semiconductor memory device
Document Type and Number:
Japanese Patent JP6107682
Kind Code:
B2
Abstract:
A semiconductor memory device includes a memory cell, a reference cell, a first current source configured to cause a first current to flow through the memory cell, a second current source configured to cause a second current having an amount thereof being variable to flow through the reference cell, a sense amplifier configured to compare a voltage responsive to a voltage drop across the memory cell with a voltage responsive to a voltage drop across the reference cell, and a current-amount setting circuit configured to determine the amount of the second current, wherein the current-amount setting circuit determines the amount of the second current such that the voltage drop across the reference cell is equal to a midpoint between the voltage drop across the memory cell having a data value of “0” stored therein and the voltage drop across the memory cell having a data value of “1” stored therein.
Inventors:
Masaki Aoki
Application Number:
JP2014010632A
Publication Date:
April 05, 2017
Filing Date:
January 23, 2014
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/15
Domestic Patent References:
| JP2009301678A | ||||
| JP11134884A | ||||
| JP2001110194A | ||||
| JP2012512499A | ||||
| JP201154248A |
Foreign References:
| WO2010082243A1 | ||||
| WO2004095464A1 |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Akinori Yamaguchi
Tadahiko Ito
Akinori Yamaguchi