Title:
暗号システム
Document Type and Number:
Japanese Patent JP7371092
Kind Code:
B2
Abstract:
A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit. The encryption circuit encrypts the plaintext input packet based on the first cryptographic parameters, and the decryption circuit decrypts the ciphertext input packet based on the second cryptographic parameters.
Inventors:
Sunka Bali, Ravi
Varma, Anujan
Pan, Chuan Chong
McCarthy, Patrick See.
Hoang, Han
Varma, Anujan
Pan, Chuan Chong
McCarthy, Patrick See.
Hoang, Han
Application Number:
JP2021516559A
Publication Date:
October 30, 2023
Filing Date:
September 11, 2019
Export Citation:
Assignee:
XILINX INCORPORATED
International Classes:
H04L9/10
Domestic Patent References:
| JP2018029267A | ||||
| JP2003324423A | ||||
| JP2004524768A | ||||
| JP2017151794A |
Foreign References:
| US20170141912 | ||||
| US20180053017 | ||||
| US20020184487 | ||||
| US20170250802 |
Attorney, Agent or Firm:
Sonoda & Kobayashi Patent Attorneys Corporation
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