Title:
電荷結合素子において一定量の電荷を減算または加算する装置
Document Type and Number:
Japanese Patent JP2008504602
Kind Code:
A
Abstract:
A circuit for adding or subtracting an amount of charge from a charge sample, such as in a Charge Coupled Device (CCD), by portioning and pipelining the processing stages, to avoid introducing a memory effect. The operation, such as subtraction, is split into multiple stages, with each stage responsible for removing only a portion of the total amount of charge that is desired to be removed. The subtraction pipeline stages operate together to remove the total desired charge amount. In one embodiment each successive subtraction stage removes a corresponding lesser amount of charge. As a result, greater accuracy in the amount of charge removed is achieved as well operation at higher frequencies than previous charge subtraction approaches.
Inventors:
Kashner Lawrence Jay
Anthony Michael Pee
Kohler Edward
Anthony Michael Pee
Kohler Edward
Application Number:
JP2007518163A
Publication Date:
February 14, 2008
Filing Date:
June 20, 2005
Export Citation:
Assignee:
KENET,INC.
International Classes:
G06G7/14; G11C19/28; H01L21/339; H01L27/148; H01L29/762
Attorney, Agent or Firm:
Shuji Sugimoto
Masashi Noda
Kenro Tsutsumi
Masashi Noda
Kenro Tsutsumi