Title:
DISTORTION COMPENSATION APPARATUS AND DISTORTION COMPENSATION METHOD
Document Type and Number:
Japanese Patent JP2018011139
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To reduce throughput in processing for suppressing accumulation of offsets.SOLUTION: A distortion compensation apparatus includes a Look Up Table (LUT) 42, a linear term coefficient table 41, a first update amount calculation section 53, an adder 52, and an adder 57. The LUT 42 stores coefficients of nonlinear terms out of coefficients of linear terms and coefficients of nonlinear terms included in filtering coefficients to be used for filtering of an input signal x(n), correspondingly to addresses other than regulated addresses found from the input signal x(n). The linear term coefficient table 41 stores coefficients of linear terms in the regulated addresses. The first update amount calculation section 53 respectively calculates update amounts of coefficients of nonlinear terms and update amounts of coefficients of linear terms on the basis of an output signal. The adder 52 updates respective coefficients in the LUT 42 on the basis of the update amounts of the coefficients of the nonlinear terms. The adder 57 updates respective coefficients in the linear term coefficient table 41 on the basis of the update amounts of the coefficients of the linear terms.SELECTED DRAWING: Figure 5
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Inventors:
MIYAZAKI TOSHIHARU
ISHIKAWA HIROYOSHI
HASE KAZUO
ISHIKAWA HIROYOSHI
HASE KAZUO
Application Number:
JP2016137151A
Publication Date:
January 18, 2018
Filing Date:
July 11, 2016
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H03F1/32; H03F3/24
Attorney, Agent or Firm:
Sakai International Patent Office
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