Title:
A false obstacle generation method and a device
Document Type and Number:
Japanese Patent JP5984197
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a device and a method in which simulated fault generation with respect to an electronic circuit device is facilitated and work such as testing and evaluation is made efficient.SOLUTION: By a control part 102 connected to an ON/OFF terminal of an IC (104) on a circuit board (105) constituting an electronic circuit device (100) via a connection 103, a PC (110) is controlled via a cable connector part (101) and a second value different from a first value during operation is set to the ON/OFF terminal of the IC (104), thereby generating simulated fault.
Inventors:
Masashi Kaneda
Application Number:
JP2011220968A
Publication Date:
September 06, 2016
Filing Date:
October 05, 2011
Export Citation:
Assignee:
NEC Communication Systems, Ltd.
International Classes:
G01R31/28; G06F11/22
Domestic Patent References:
| JP56082676U | ||||
| JP63286939A |
Attorney, Agent or Firm:
Kato Asamichi
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