Title:
The flip-flop for reducing dynamic electric power
Document Type and Number:
Japanese Patent JP6246903
Kind Code:
B2
Abstract:
A flip-flop circuit may include a first latch and a second latch. The first latch, which may operate as a “master” latch, includes a first input terminal to receive a data signal, a second input terminal to receive a clock signal, and an output terminal. The second latch, which may operate as a “slave” latch, includes a first input terminal connected directly to the output terminal of the first latch, a second input terminal to receive the clock signal, and an output terminal to provide an output signal. The first latch and the second latch are to be clocked on the same phase of the clock signal, thereby eliminating the need to include clock inversion circuits that generate complementary clock signals.
Inventors:
Kai, Yang Fei
Dai, Kian
Fan, suanq
Dai, Kian
Fan, suanq
Application Number:
JP2016512183A
Publication Date:
December 13, 2017
Filing Date:
May 08, 2013
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H03K3/037; H03K3/3562
Domestic Patent References:
| JP2011171916A | ||||
| JP11340957A | ||||
| JP2012156821A | ||||
| JP2001308686A |
Foreign References:
| US20040027184 |
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Morisezo Iseki
Okumura Motohiro
Yoshihiro Fukuhara
Morisezo Iseki
Okumura Motohiro