Title:
ゲート駆動回路
Document Type and Number:
Japanese Patent JP7356340
Kind Code:
B2
Abstract:
Provided is a gate drive circuit that is provided with an active clamp for protecting portions between a collector and an emitter of an IGBT, that suppresses heat generation of a constant voltage diode, and that generates a limited amount of noise. This gate drive circuit is provided with a clamp circuit that clamps a voltage between a collector (hereinafter referred to as C) and an emitter (hereinafter referred to as E) of a power semiconductor element. The clamp circuit has: a constant voltage diode (hereinafter referred to as D) connected to C; an impedance circuit connected between the other end of the constant voltage D and a minus power supply; a first drawing circuit that has one end connected to a connection point between the constant voltage D and the impedance circuit and that comprises a first switch (hereinafter referred to as SW) and a first resistor; a second drawing circuit that comprises the second SW and a second resistor that are connected in a similar manner to the connection regarding the first drawing circuit; and a detection circuit that, when a change rate of a C voltage has exceeded a threshold value, outputs a SW open signal. When the SW open signal has been received, the second SW is changed from a conduction state to a non-conduction state.
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Inventors:
Hiroo Ogawa
Application Number:
JP2019234486A
Publication Date:
October 04, 2023
Filing Date:
December 25, 2019
Export Citation:
Assignee:
Tamura Manufacturing Co., Ltd.
International Classes:
H03K17/08; H02M1/00; H02M1/08; H03K17/082; H03K17/16; H03K17/567
Domestic Patent References:
| JP2014165939A | ||||
| JP2002135097A | ||||
| JP2013126278A | ||||
| JP2017152923A | ||||
| JP2008035067A |
Foreign References:
| US10505538 | ||||
| US20140015571 |
Attorney, Agent or Firm:
Mitsuru Ito
Koichiro Matsumoto
Junichi Yoshida
Koichiro Matsumoto
Junichi Yoshida