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Title:
モノリシックなシリコンベースの光電子回路の設計、シミュレーション、及び検査用の統合的アプローチ
Document Type and Number:
Japanese Patent JP2008509452
Kind Code:
A
Abstract:
Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product ("tape out").

Inventors:
Carpentry
Pasak, Soham
Goat Scar, Prakash
Mosinskis, Paulius
Dama, Bipin
Application Number:
JP2007518269A
Publication Date:
March 27, 2008
Filing Date:
June 22, 2005
Export Citation:
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Assignee:
Cioptical Incorporated
Chasli, Carpendu
Pasak, Soham
Goat Scar, Prakash
Mosinskis, Paulius
Dama, Bipin
International Classes:
G06F17/50; G06G7/62
Domestic Patent References:
JP2001230638A2001-08-24
JP2005174153A2005-06-30
JP2005174154A2005-06-30
JP2001230638A2001-08-24
JP2005174153A2005-06-30
JP2005174154A2005-06-30
Attorney, Agent or Firm:
Mieko Kashihara