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Patent Searching and Data


Title:
INTEGRATED CIRCUIT PACKAGE
Document Type and Number:
Japanese Patent JPH065733
Kind Code:
A
Abstract:

PURPOSE: To dispose pins on an entire lower surface of a package in which an integrated circuit chip is mounted downward on a front surface.

CONSTITUTION: An integrated circuit chip 6 is mounted downward on a front surface in a ceramic package 1, and electrically connected to the package 1. A signal wire from the chip 6 is wired to a connecting pad 1a of a lower surface of the package l through a wiring pattern in the package 1. A connecting pad 1a on the lower surface of the package 1 is connected to a connecting pad 2a of the same array of the upper surface of a sealing plate 2 by soldering. The pads 2a on the upper surface of the plate 2 are so electrically connected to pins 3 of the lower surface as to correspond through a wiring pattern 2b in the plate 2. After the pad 1a is connected to the pad 2a, the package 1 and the plate 2 are hermetically sealed with sealing material 4.


Inventors:
TAKAHASHI YUTAKA
Application Number:
JP18299592A
Publication Date:
January 14, 1994
Filing Date:
June 17, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L23/12; H01L23/50; (IPC1-7): H01L23/12; H01L23/50
Attorney, Agent or Firm:
Yanagi Kawa Shin