Title:
A manufacturing method of a thin film semiconductor board, a luminescence panel, and a thin film semiconductor board
Document Type and Number:
Japanese Patent JP5948427
Kind Code:
B2
Abstract:
A thin-film semiconductor substrate includes a top-gate first TFT, a top-gate second TFT, and a data line (source line), in which the first TFT has a first semiconductor layer, a first gate insulating film, a first gate electrode, a first source electrode, a first drain electrode, and a first protection layer, the second TFT has a second semiconductor layer, a second gate insulating film, a second gate electrode, a second source electrode, a second drain electrode, and a second protection layer, the data line is connected to the first source electrode, the first drain electrode is an extension of the second gate electrode, and the second gate electrode is thinner than the data line.
Inventors:
Arigousu Kanegae
Kiyoyuki Morita
Kiyoyuki Morita
Application Number:
JP2014538007A
Publication Date:
July 06, 2016
Filing Date:
February 21, 2014
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
G09F9/30; G09F9/00; H01L21/28; H01L21/768; H01L23/522; H01L27/32; H01L29/417; H01L29/423; H05B33/10; H05B44/00
Domestic Patent References:
| JP2010156963A | 2010-07-15 | |||
| JP2003233088A | 2003-08-22 | |||
| JPH0981053A | 1997-03-28 | |||
| JPH10161564A | 1998-06-19 | |||
| JP2002352955A | 2002-12-06 |
Attorney, Agent or Firm:
Hiromori Arai
Eisaku Teratani
Shinichi Michisaka
Eisaku Teratani
Shinichi Michisaka
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