Title:
メモリシステム
Document Type and Number:
Japanese Patent JP7419113
Kind Code:
B2
Abstract:
A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read a received word from the non-volatile memory, estimate noise by using a plurality of different models for estimating the noise included in the received word to obtain a plurality of noise estimation values, select one noise estimation value from the plurality of noise estimation values, update the received word by using a value obtained by subtracting the selected noise estimation value from the read received word, and decode the updated received word by using a belief-propagation method.
Inventors:
Yuma Yoshinaga
Tomoya Kodama
Osamu Torii
Kenichiro Furuta
Ryuta Yoshizawa
Tomoya Kodama
Osamu Torii
Kenichiro Furuta
Ryuta Yoshizawa
Application Number:
JP2020037936A
Publication Date:
January 22, 2024
Filing Date:
March 05, 2020
Export Citation:
Assignee:
Kioxia Corporation
International Classes:
H03M13/19; G06F11/10; H03M13/47
Domestic Patent References:
| JP2016181738A |
Foreign References:
| US20190288878 |
Other References:
Fei Liang et al.,An Iterative BP-CNN Architecture for Channel Decoding,IEEE Journal of Selected Topics in Signal Processing,2018年01月15日,Vol.12, No.1,pp.144-159
Attorney, Agent or Firm:
Sakai International Patent Office