Title:
フローティングアイランドを形成するための雛壇状のトレンチを備えた電圧維持層を有するパワー半導体デバイスの製造方法
Document Type and Number:
Japanese Patent JP2011505709
Kind Code:
A
Abstract:
A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region. A filler material is deposited in the terraced trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.
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Inventors:
Blanchard, Richard, A.
Gilot, Jean-Michelle
Gilot, Jean-Michelle
Application Number:
JP2010537046A
Publication Date:
February 24, 2011
Filing Date:
December 04, 2008
Export Citation:
Assignee:
Vishay General Semiconductor LLC
International Classes:
H01L29/78; H01L21/336
Domestic Patent References:
| JP2005505918A | 2005-02-24 | |||
| JPS62203380A | 1987-09-08 |
Attorney, Agent or Firm:
▲吉▼川 俊雄