Title:
スケジューラキュー割り当てバーストモード
Document Type and Number:
Japanese Patent JP7292515
Kind Code:
B2
Abstract:
Systems, apparatuses, and methods for implementing scheduler queue assignment burst mode are disclosed. A scheduler queue assignment unit receives a dispatch packet with a plurality of operations from a decode unit in each clock cycle. The scheduler queue assignment unit determines if the number of operations in the dispatch packet for any class of operations is greater than a corresponding threshold for dispatching to the scheduler queues in a single cycle. If the number of operations for a given class is greater than the corresponding threshold, and if a burst mode counter is less than a burst mode window threshold, the scheduler queue assignment unit dispatches the extra number of operations for the given class in a single cycle. By operating in burst mode for a given operation class during a small number of cycles, processor throughput can be increased without starving the processor of other operation classes.
Inventors:
Alok Garg
Scott Andrew McClelland
Marius Evers
Matthew T. Sobel
Scott Andrew McClelland
Marius Evers
Matthew T. Sobel
Application Number:
JP2022534256A
Publication Date:
June 16, 2023
Filing Date:
December 08, 2020
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INCORPORATED
International Classes:
G06F9/38; G06F9/318
Domestic Patent References:
| JP2004532444A |
Foreign References:
| WO2019231904A1 |
Attorney, Agent or Firm:
Yuji Hayakawa
Ryota Sano
Keisuke Murasame
Ryota Sano
Keisuke Murasame