Title:
半導体装置
Document Type and Number:
Japanese Patent JP7137913
Kind Code:
B2
Abstract:
To reduce an area occupied by peripheral circuits of a storage device, and provide a storage device having a large storage capacity per unit area.SOLUTION: A semiconductor device is provided with a memory cell array and a circuit section including a high withstand voltage transistor on the same substrate. The memory cell array has a structure in which a plurality of memory transistors are stacked in the vertical direction. A semiconductor layer included in the memory transistor and a semiconductor layer included in a transistor with a high withstand voltage are formed by processing the same semiconductor film. Further, an oxide semiconductor is applied to a semiconductor layer included in each of the memory transistor and the transistor with high withstand voltage.SELECTED DRAWING: Figure 1
Inventors:
Takanori Matsuzaki
Kensuke Yoshizumi
Kensuke Yoshizumi
Application Number:
JP2017123146A
Publication Date:
September 15, 2022
Filing Date:
June 23, 2017
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/336; H01L21/8242; H01L27/108; H01L27/11556; H01L27/1156; H01L27/11582; H01L29/786; H01L29/788; H01L29/792
Domestic Patent References:
| JP2017092432A | ||||
| JP2017034144A | ||||
| JP2016063027A | ||||
| JP2012248823A | ||||
| JP2011108882A | ||||
| JP2013247143A |
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