Title:
半導体装置
Document Type and Number:
Japanese Patent JP7285983
Kind Code:
B2
Abstract:
It is an object to form a buffer circuit, an inverter circuit, or the like using only n-channel TFTs including an oxide semiconductor layer. A buffer circuit, an inverter circuit, or the like is formed by combination of a first transistor in which a source electrode and a drain electrode each overlap with a gate electrode and a second transistor in which a source electrode overlaps with a gate electrode and a drain electrode does not overlap with the gate electrode. Since the second transistor has such a structure, the capacitance Cp can be small, and VA′ can be large even in the case where the potential difference VDD−VSS is small.
Inventors:
Hiroyuki Miyake
Application Number:
JP2022045455A
Publication Date:
June 02, 2023
Filing Date:
March 22, 2022
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/336; G09F9/30; H01L29/786
Domestic Patent References:
| JP2010171404A | ||||
| JP20017342A | ||||
| JP2009290224A | ||||
| JP201186929A |