Title:
Post-layout circuit yield verification method, yield verification program and yield verification device
Document Type and Number:
Japanese Patent JP6318897
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To achieve the efficiency of the yield verification of a post-layout circuit by performing the necessary number of times of simulation with respect to requested accuracy.SOLUTION: A computer executes a process (step A3) of executing post-layout simulation one time; a process (step S4) of calculating difference data between performance variation data by pre-layout simulation and the post-layout simulation; process (step A5) of calculating yield prediction accuracy by using the difference data; a process (step A6) of determining whether or not the yield prediction accuracy has reached requested accuracy; and a process (step A8) of repeatedly executing the post-layout simulation execution process, the difference data calculation process, the yield prediction accuracy calculation process and the determination process until it is determined that the yield prediction accuracy has reached the requested accuracy, and calculating a yield predictive value when it is determined that the yield prediction accuracy has reached the requested accuracy.
Inventors:
Liu U
Application Number:
JP2014124387A
Publication Date:
May 09, 2018
Filing Date:
June 17, 2014
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F17/50
Domestic Patent References:
| JP2012203714A | ||||
| JP2003006263A | ||||
| JP2011113291A |
Attorney, Agent or Firm:
Yu Sanada
Masahisa Yamamoto
Masahisa Yamamoto