Field of the Invention

This invention relates to an analogue to digital converter (ADC).

Background Art

Some of the problems associated with ADC level inaccuracy noise in a multi-bit feedback coder were discussed in the specification accompanying copending patent application No. 8820878, filed 6th September 1988 (F20557). Particular techniques to overcome these problems were proposed. The specification explained that a fundamental difficulty with this type of circuit is that a multi-bit digital to analogue converter (DAC) is required at the end of the feedback loop. Any noise associated with level inaccuracy in this DAC is unaffected by the loop action. Thus as described in the patent application it is desirable to use only a two level (one-bit) DAC so that any inaccuracy in the DAC levels can be compensated for by the addition of a small number of external components. The patent specification referred to techniques whereby a multi-bit quantiser could have its output truncated to provide a single-bit feedback signal, and digital signal processing after the coder as a whole,

could correct for the effects of this truncation.

Summary of the Invention

As level inaccuracy of the DAC may be dealt with by the techniques described in British Patent Application No. 8820878, there remains to be considered the subsidiary problem of level inaccuracy in the quantising element, and techniques by which this may be overcome.

Inaccuracies in the transfer function of the quantising element may be sub-divided into two categories, depending on whether they affect a very small, or a more extensive region of the characteristic. Local inaccuracies affecting only one (or at most two) of the quantiser levels are known as differential non -linearities. Their spectrum is generally white, similar to the quantisation error, so they add to the latter in an uncorrelated manner and are shaped by the loop action in exactly the same way. In most practical situations, the magnitude of the differential non-linearities is of the same order, or is smaller than the qunatisation errors. For this reason these will only add up to around 3dB increase in the in-band noise power and have an essentially white spectrum, so that they are not too significant.

Errors in the quantiser characteristic which extend over a significant number of quantising levels, lead to a distortion of the input signal. The resulting distortion components may occur in-band and so be unaffected by loop action. For example, if the quantiser has n-bit resolution, and the transfer characteristic has a simple quadratic component, resulting in an m-bit deviation at the centre of the transfer curve, then a first harmonic will be present which will be approximately 20 log(m/2 ⁿ ) down on the fundamental. The existence of such spuriae may limit the usable dynamic range of the coder as a whole.

The present invention was devised in order to reduce these level inaccuracies in the transfer function of the quantising element.

According to the invention, there is provided an analogue

to digital converter circuit of the kind including an n-bit quantiser (where n^l) for providing an output signal comprising an n-bit representation of the signal applied to its input, in which the quantiser is replaced by a quantiser element providing an address location and a random access memory (RAM) device at which an accurate representation of the corresponding output signal is stored, thus providing an instantaneous output signl of a predetermined level accuracy.

The RAM device may be arranged such that the stored signal values are of greater accuracy than those output by the quantiser element.

The present invention has particular application in oversa pled ADC, in which sampling speed is far greater than the nyquist sampling frequency, since the inherent delay created in accessing the RAM is Inconsequential.

It is necessary to correctly calibrate the RAM at some stage. Typically the write cycle of a RAM may be 1 ns, whereas a convrsion cycle of an ADC may be 100 ns. This means that a calibration cycle of the ADC may be carried out at any time without significantly delaying the operation of the ADC.

As preferred the ADC according to the invention is of the type described and claimed in British Patent application 8820878.0, namely, an analogue-to-digital converter circuit comprising a differencing means for comparing an analogue input signal and a feedback signal to provide an output dependent on the difference between the signals, a feed-forward filter coupled to receive the differencing means output for providing low-frequency preemphasis, and coupled to the input of an n-bit quantiser (where n^> 1) for providing an output signal comprising an n-bit representation of the signal applied to its input, a means for truncating the quantiser output signal to the MSB and for providing a feedback signal whose value is dependnt on the MSB, a feedback filter means coupled to receive the feedback signal and provide it to the differencing means, and correction means for providing a correction signal for combining with the quantiser output signal, to provide a converter circuit output signal which compensates for the effect of the truncation in

the feedback loop; or an anlogue-to-digital converter circuit comprising means for selectively inverting an input signal and feeding the signal via a feedforward filter providing low frequency pre-emphasis to an n-bit quantiser (where n)l) for providing an output signal comprising an n-bit representation of the signal applied to its input, a means for truncating the quantiser output signal to the MSB and providing a feedback signal whose value is dependent on the MSB, a feedback filter means coupled to receive the feedback signal and to provide it to the selective inversion means for control thereof, and correction means for correcting the quantiser output signal to provide a converter circuit output signal which compensates for the effect of the selective inversion of the input signal.

Brief Description of the Drawings

By way of example, some particular embodiments of the invention will now be described with reference to the accompanying drawings, in which:

Figures 1 and 2 are block diagrams of different quantiser-calibrated feedback coders according to the invention; and

Figure 3 is a block diagram of an ADC in which the present invention may be utilized.

Description of the Preferred Embodiments

The level in accuracy problem may be reduced, according to the present invention, by regarding the quantiser output not as a direct representation of the analogue signal at its input, but rather as an address location at which an accurate representation of the signal is stored. In general, this means that the memory word length will be substantially longer than the quantiser output word length in order that the former can give a more accurate value for the instantaneous signal value. Effectively, using a memory in this way transforms an n-bit resolution, n-bit accurate (more or less)

quantising element into an n-bit resolution, m-bit accurate component, where is the memory word length.

In order that the values stored in RAM may be more accurate than those output by the quantiser, it is necessary that the latter be calibrated, either on power-up, on command, or at suitable working intervals. A typical calibration technique would use an m-bit counter and integrator, in a slope integration method. Since all noise-shaping coders already incorporate analogue integrators the only additional component required is an m-bit counter. The calibration procedure is as follows: the m-bit counter starts at zero and increments whilst the n-bit output code of the quantiser is monitored. When the quantiser output code changes, the counter value m*ι is stored in RAM at the location n^. This procedure is repeated for all the 2 ⁿ quantiser output codes.

Such a procedure will result n an n-bit resolution m-bit accurate quantising element in which the output codes are unlikely to be equally spaced. However, this factor is unimportant provided the values are known. It should be possible to improve the accuracy of a bipolar quantiser from around 8 bits to around 14 bits, and for a CMOS quantiser fromaround 6 or 7 bits to around 10 or 12 bits. This will have a significant effect on the spurious-free dynamic range of the coder as a whole.

As shown in the drawing, the feedback coder comprises a digital to analogue converter 1 which is connected to a loop with a noise-shaping filter 2 and quantiser element 3. An output from the quantiser element 3 is delivered to a RAM device 4 and from there the output passes to a truncation correction device 6.

In order to permit calibration of the quantiser element 3, a calibration signal produced by a signal generator 7 comprising an m-bit conter 8 and an ADC 9 may be delivered into the loop when required. This signal may be inserted by means of a two way switch located either before (Figure 1) or after (Figure 2) the noise-shaping filter 2. Thus the m-bit counter 8 provides an output to ADC 9 which is connected to an analogue value and applied to the input of quantiser 3. At the same time the digital value of counter 8 is stored in RAM 4, at an address determined by the output

of quantiser 3.

Referring now to Figure 3, an input signal S is fed via a differencing circuit 20 to an integrator 22 which is indicated inconventional z-transform form as z/(z-l). An n-bit quantiser 24 digitises the input signal, introducing noise q(z). A one bit truncated version of the output signal is fed back via a delay circuit 26, indicated as z ^" to the differencing circuit 20 where it is subtracted from the input. A truncation error signal T is introduced in the feedback loop at 32 to account for the truncation of the n-bit quantiser output signal to the MSB. The truncation error signal is a known quantity; it is the quantiser output with the MSB removed. The quantiser 24 is an n-bit quantiser, where n l and n<^7, in accordance with current technical limits.

Loop analysis yields the transfer relation

a(z) = s(z) + ( z - 1 ) * q(z) / z - T(z) / z (3)

The truncation error term in the output signal can be cancelled by adding a delayed version of itself at the output, shown in Figure 3 in which truncation signal T is delayed in unit 34 and added to the output in an adder 36. Thus:

y(z) = a(z) + T(z) / z = s(z) + ( z - 1) * q(z) / z (4)

This expression is identical to that which would be obtained for a conventional single-bit coder of first order, with the important exception that, the noise term is that appropriate to a multi-bit quantiser. Relative to a single-bit system, such multi-bit quantiser with single-bit feedback, will reduce the unshaped noise by approximately 6 * ( n - 1), where n is the quantiser resolution. This reduction takes place in addition to the benefits which accrue from both noise-shaping and oversampling.

The circuit of Figure 3 may incorporate the present invention by addition of RAM 4 and signal generator 7 as indicated in dotted lines.