Title:
ARITHMETIC PROCESSING UNIT, INFORMATION PROCESSING DEVICE, AND ARITHMETIC PROCESSING UNIT CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2012/172683
Kind Code:
A1
Abstract:
On the basis of a memory access request inputted from a request storage unit (0) through a CPU core unit, an L2 cache control unit searches cache memory and holds in a request storage unit (1) and a request storage unit (2) memory access requests generated by cache misses. A bank abort generation unit calculates for each bank the number of memory access requests to a main storage device on the basis of the memory access requests stored in the request storage units (1 and 2), and, if the calculated number of memory access requests for any of the banks exceeds a prescribed value, sends an access interruption command by sending a bank abort notification to the L2 cache control unit. On the basis of that command, the L2 cache control unit interrupts the processing of memory access requests held in the request storage unit (2). The main storage control unit issues to the main storage device the memory access request stored in the request storage unit (2).
Inventors:
HIKICHI TORU (JP)
Application Number:
PCT/JP2011/063926
Publication Date:
December 20, 2012
Filing Date:
June 17, 2011
Export Citation:
Assignee:
FUJITSU LTD (JP)
HIKICHI TORU (JP)
HIKICHI TORU (JP)
International Classes:
G06F12/08; G06F12/06; G06F12/0811; G06F12/0846
Foreign References:
| JP2009205573A | 2009-09-10 | |||
| JPH1185605A | 1999-03-30 |
Other References:
MASAAKI KONDO ET AL.: "Traction Control Execution : Optimizing Thread Execution in CMPs", IPSJ SIG NOTES, vol. 2007, no. 79, 3 August 2007 (2007-08-03), pages 79 - 84, XP008171038
KYLE J. NESBIT ET AL.: "Fair Queuing Memory Systems", PROCEEDINGS OF THE 39TH ANNUAL IEEE/ ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, 13 December 2006 (2006-12-13), pages 208 - 222, XP031034172
KYLE J. NESBIT ET AL.: "Fair Queuing Memory Systems", PROCEEDINGS OF THE 39TH ANNUAL IEEE/ ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, 13 December 2006 (2006-12-13), pages 208 - 222, XP031034172
Attorney, Agent or Firm:
OSUGA, Yoshiyuki (JP)
Yoshiyuki Osuge (JP)
Yoshiyuki Osuge (JP)
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Claims: