MCCALPIN WILLIAM H
WONG RICKEY C
| JPS60165759A | 1985-08-28 |
| 1. | A bipolar transistor for use in Class A and Class AB linear amplifiers with reduced third order and higher harmonic frequency distortion of an input signal comprising: a semiconductor substrate of a first conductivity type and a first dopant concentration, an epitaxial layer of said first conductivity type formed on said semiconductor substrate and having an exposed major surface, said epitaxial layer having a second dopant concentration less than said first dopant concentration, a base region of a second conductivity type formed in said epitaxial layer abutting said surface, said base region having a thickness, T, and at least one emitter region of said first conductivity type formed in said base region and abutting said surface, said emitter region having a width, W, with a ratio of emitter width to base thickness being in the range of 3 to 4. |
| 2. | The bipolar transistor as defined by Claim 1 wherein said second dopant concentration provides a high resistivity and a low output capacitance for said transistor. |
| 3. | The bipolar transistor as defined by Claim 2 wherein said first conductivity type is Ntype, and said second conductivity type is Ptype. |
| 4. | The bipolar transistor as defined by Claim 3 wherein said first conductivity type is provided by arsenic dopant and such second conductivity type is provided by boron dopant. |
| 5. | The bipolar transistor as defined by Claim 4 wherein said first dopant concentration is on the order of 1019 cm"3, said second dopant concentration is on the order of 2.5 x 1016 atoms cm"3, said base region has a thickness on the order 0.6 micron and a dopant concentration on the order of 5 x 1018 cm"3, and said emitter region has a width on the order of 2.0 microns and a dopant concentration on the order of 1021 atoms cm"3. |
| 6. | The bipolar transistor as defined by Claim 5 and further including metal finger contacts to said base region and a metal finger contact to said emitter region. |
| 7. | The bipolar transistor as defined by Claim 6 wherein said semiconductor material is silicon. |
| 8. | The bipolar transistor as defined by Claim 1 and further including metal finger contacts to said base region and a metal finger contact to said emitter region. |
| 9. | The bipolar transistor as defined by Claim 8 wherein said semiconductor material is silicon. |
BACKGROUND OP THE INVENTION
This invention relates generally to linear amplifiers, and more particularly the invention relates to a bipolar transistor for use in a linear amplifier which reduces harmonic distortion. An ideal linear amplifier is one that has a transfer function of the form where output signal is a constant amplification of the input signal, or P out = AP in where A is constant over the entire useful power range of the amplifier. However, in practice, amplifiers exhibit various degrees of non-linearity due to device and circuit construction which produce unwanted distortion when amplifying signals.
A number of design criteria have been proposed in the past to reduce distortion in linear amplifiers operating with bipolar junction transistors such as operating the devices in a push-pull form, matching device forward current gain ( / 3) , operating the device in as large a forward bias (more to Class A) as possible, and operating the device in complex circuits with feed forward and feedback.
Any device embedded in a real amplifier will generate a number of intermodulation products when driven with an input signal composed of multiple frequencies. Second order distortion products can be generally minimized by circuit construction, so the interest in distortion reduction at the device level begins with third order and higher products. For example, the amplifier illustrated in Fig. 1A has a two-tone input signal of equal amplitude as illustrated in Fig. IB, which will produce four third order intermodulation products (2f x ± f 2 and 2f 2 ± f α ) , along with the amplified input signal ( f χ , f 2 ) as illustrated in Fig. IC. However, only the difference products are typically considered
since sum products typically fall outside of the amplifier bandwidth.
Traditionally, bipolar junction transistor devices have been designed on the basis of emitter perimeter utilization, large ballast resistors, and low parasitic capacitances which are all good conditions to achieve large power output capability. However, typical devices experience a "hill and valley" on the third order distortion curve as shown in Fig. 2 that limits the minimum distortion values in the operating dynamic range to the maximum value of distortion encountered on the "hill" of the curve. For example, if a device designed to operate as a driver in a Class AB linear amplifier for cellular base station applications has to maintain third order distortion products better than 40dB below the fundamental carrier frequencies (or dBc) when operated at rated power or below, then the design of a Class AB driver device requires a "hill" of 40dBc or better.
In accordance with the invention, the "hill and valley" behavior is believed to be related to a non-linearity in the value of the intrinsic base resistance (Rbb) that is also related to the onset of the current crowding of the emitter fingers. This variation in the intrinsic base resistance (Rbb) occurs at low power inputs and is believed to be a direct result of the side wall component of the base current. This side wall component is due to emitter-base space charge and surface recombination. Modern high power, high frequency bipolar transistors are designed with a large perimeter/area ratio emitter which increases the relative importance of this base current component which has been demonstrated by computer simulation as shown in Fig. 3 to effect the size and magnitude of the "hill" in the power transfer curve.
Based on these considerations, the present invention is directed to a bipolar transistor device design and fabrication process which minimizes sources of third order and higher non-linearity.
SUMMARY OF THE INVENTION In accordance with the invention, a bipolar junction transistor is provided which has a ratio of emitter width to base depth between three and four which has proved to be optimum in minimizing emitter current crowding over a large range of low base current values while maintaining large intrinsic gain. Additionally, ballast resistance of the device is minimized, contingent to the demand that the device be sufficiently rugged to sustain a device output impedance mismatch. The resulting device provides reduced distortion in third order and higher intermodulation products.
The invention and objects and features thereof will be more readily apparent from the following detailed description and dependent claims when taken with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A, IB, and IC illustrate a convention non¬ linear amplifier, two-tone input signals, and output signals including third order intermodulation products, respectively. Fig. 2 is a graph illustrating third order distortion.
Fig. 3 is a computer simulated plot of side wall base current (Ise) and third order intermodulation output Power (dBc) vs. Carrier Output Power. Fig. 4 is a side view in section illustrating the structure of bipolar junction transistor in accordance with the invention.
Figs. 5A-5D are section views illustrating a process in accordance with the invention for fabricating the device of Fig. 4.
DETAILED DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENT Fig. 4 is a section view of a bipolar junction transistor in accordance with one embodiment of the invention for realizing reduced third harmonic intermodulation distortion in a linear amplifier. The device includes a substrate 10 of N-doped silicon with an N-doped epitaxial layer 11 formed thereon. As is conventional, epitaxial
layer 11 forms the collector region of the bipolar transistor and is of high resistivity and sufficiently thin to provide constant and low output capacitance. A p-ring 21 surrounds the active transistor region for breakdown enhancement, and a p base region 24 extends from ring 21 across the surface of the epitaxial layer 11. Shallow N-doped emitter regions 25 are then formed in the surface of the base region 24, and emitter contact fingers 30 contact the emitter regions 25 through openings in silicon oxide layer 20 along with the base contact fingers 32.
Fabrication of the device of Fig. 4 is illustrated in the section views of Figs. 5A through 5D. In Fig. 5A, the process starts with an N-type silicon substrate 10 having an arsenic dopant concentration on the order of 10 19 cm "3 on which a very thin epitaxial N- layer 11 is grown to define the material characteristics responsible for collector-base breakdown voltage and capacitance. The dopant concentration in epitaxial layer 11 will be on the order of 2.5 x lθ 16 cm "3 and the thickness of the epitaxial layer will be on the order of four microns. A silicon oxide layer 20 is then grown or deposited on the surface of the epitaxial layer 11.
Next, as shown in Fig. 5B a standard photo resist masking technique is used to define an opening through oxide layer 20 to expose the silicon surface area into which is diffused or implanted a p-dopant, boron for example, to form the p-ring 21. P-ring 21 enhances breakdown of the transistor region within the ring and the p-type dopant is diffused to a desired depth, such as one and a half microns. A second opening is formed inside the ring area and the p-type base 24 is formed by diffusion or by implantation of boron dopant on the order of 5xl0 18 atoms cm "3 to the desired depth such as 0.6 micron as shown in Fig. 5C. Oxide is then regrown or deposited over the base region. A composite mask with both emitter and base contact openings is etched in the oxide covering the base, and an N-type dopant such as arsenic is implanted to form the emitter 25 having a width on the order of 2.0 microns and dopant concentration on the order of 10 21 atoms cm "3 using an enlarged opening emitter resist layer 27
as a protective mask as shown in Fig. 5D. After the photo resist is removed and the emitter implant thermally activated, the device is completed by depositing or sputtering the emitter and base metal fingers and bonding pads as shown in Fig. 4.
The described bipolar junction transistor in which the ratio of emitter width to the base depth is between 3 and 4 minimizes emitter current crowding over a large range of low base current values while maintaining large intrinsic gain. The ballast resistance in the fabrication approach is made as small as possible contingent on the demand that the device be rugged enough to sustain the desired output impedance mismatch. Accordingly, third order and higher intermodulation distortion is significantly reduced to provide improved Class A and Class AB RF power amplifiers.
While the invention has been described with reference to a specific embodiment, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications and changes might occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.