Title:
CALCULATION DEVICE AND TEST METHOD
Document Type and Number:
WIPO Patent Application WO/2022/102220
Kind Code:
A1
Abstract:
This calculation device executes a test using a partially reconfigurable programmable logic unit. In the programmable logic unit, a test target circuit that is a user circuit and a non-test circuit that is a user circuit that is not the test target circuit are configured. The calculation device is provided with: a configuration control unit that causes a test partition unit for separating the test target circuit from the non-test circuit to be formed in the programmable logic unit by partial reconfiguration; and a partition control unit that controls the test partition unit in order to test the test target circuit.
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Inventors:
IKEDA YASUHIRO (JP)
TOBA TADANOBU (JP)
SHIMBO KENICHI (JP)
ARATA ATSUSHI (JP)
YAMASHITA TAKEO (JP)
ICHIGE ATSUSHI (JP)
NONAKA SHINICHI (JP)
TOBA TADANOBU (JP)
SHIMBO KENICHI (JP)
ARATA ATSUSHI (JP)
YAMASHITA TAKEO (JP)
ICHIGE ATSUSHI (JP)
NONAKA SHINICHI (JP)
Application Number:
PCT/JP2021/032024
Publication Date:
May 19, 2022
Filing Date:
August 31, 2021
Export Citation:
Assignee:
HITACHI ASTEMO LTD (JP)
International Classes:
G01R31/28; H01L21/82; H01L21/822; H01L27/04
Foreign References:
| JP2010054402A | 2010-03-11 | |||
| JP2007264995A | 2007-10-11 | |||
| JP2001144261A | 2001-05-25 | |||
| JPH1144741A | 1999-02-16 |
Attorney, Agent or Firm:
SUNNEXT INTERNATIONAL PATENT OFFICE (JP)
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