Title:
CAPACITANCE MEASUREMENT METHOD BASED ON DELAY PHASE-LOCKED LOOP AND CAPACITANCE MEASUREMENT CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2024/067590
Kind Code:
A1
Abstract:
A capacitance measurement method based on a delay phase-locked loop and a capacitance measurement circuit. The method comprises: when a capacitance measurement circuit is in an open-loop state, carrying out delay processing on a reference clock signal by means of a first capacitor (Cx) to obtain a first delay signal; carrying out delay processing on a first input signal of an elimination path and the reference clock signal by means of a second capacitor (Cc) to obtain a second delay signal, the first input signal being an output signal of a main path when the capacitance measurement circuit is stable in a closed-loop state; and inputting the first delay signal and the second delay signal into the main path so as to obtain an output signal of the main path at a current time step, and according to the output signal of the main path at the current time step, calculating a change value of the first capacitor (Cx).
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Inventors:
BAI SONGRONG (CN)
FAN SHUO (CN)
ZHANG HAIYUE (CN)
FAN SHUO (CN)
ZHANG HAIYUE (CN)
Application Number:
PCT/CN2023/121579
Publication Date:
April 04, 2024
Filing Date:
September 26, 2023
Export Citation:
Assignee:
SHENZHEN CVA INNOVATION CO LTD (CN)
International Classes:
G01R27/26; G06F3/041; H03K17/96
Foreign References:
| CN115616294A | 2023-01-17 | |||
| CN115575718A | 2023-01-06 | |||
| CN115575719A | 2023-01-06 | |||
| CN114355056A | 2022-04-15 | |||
| CN114356145A | 2022-04-15 | |||
| CN105071799A | 2015-11-18 | |||
| CN111130341A | 2020-05-08 | |||
| CN111398689A | 2020-07-10 | |||
| KR20130050458A | 2013-05-16 | |||
| US4968946A | 1990-11-06 |
Attorney, Agent or Firm:
ADVANCE CHINA IP LAW OFFICE (CN)
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