Title:
CELL-BASED SWITCH FABRIC ARCHITECTURE ON A SINGLE CHIP
Document Type and Number:
WIPO Patent Application WO2002098066
Kind Code:
A3
Abstract:
A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the cells for permitting exchange of data packet between the cells and components external thereto. Each cell includes a transmitter in communication with the I/O interface and in communication with every other cell of the array, the transmitter being operative to process a data packet received from the I/O interface to determine a destination of the packet and forward it to at least one cell of the array selected on a basis of the determined destination. Each cell further includes plural receivers associated with respective cells from the array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver, where the receivers are in communication with the I/O interface for releasing data packets thereto. In this way, the transmitter in a given cell functionally extends into those cells where dedicated receivers are located, reducing transmitter memory requirements and allowing the switch fabric to be implemented on a single chip.
Inventors:
NORMAN RICHARD S (CA)
DE MARIA MARCELO (CA)
COTE SEBASTIEN (CA)
LANGLOIS CARL (CA)
HAUGHEY JOHN (US)
BOUDREAULT YVES (CA)
DE MARIA MARCELO (CA)
COTE SEBASTIEN (CA)
LANGLOIS CARL (CA)
HAUGHEY JOHN (US)
BOUDREAULT YVES (CA)
Application Number:
PCT/CA2002/000810
Publication Date:
September 25, 2003
Filing Date:
May 31, 2002
Export Citation:
Assignee:
HYPERCHIP INC (CA)
NORMAN RICHARD S (CA)
DE MARIA MARCELO (CA)
COTE SEBASTIEN (CA)
LANGLOIS CARL (CA)
HAUGHEY JOHN (US)
BOUDREAULT YVES (CA)
NORMAN RICHARD S (CA)
DE MARIA MARCELO (CA)
COTE SEBASTIEN (CA)
LANGLOIS CARL (CA)
HAUGHEY JOHN (US)
BOUDREAULT YVES (CA)
International Classes:
H04L49/111; (IPC1-7): H04L12/56
Domestic Patent References:
| WO1998026539A2 | 1998-06-18 |
Foreign References:
| EP1051001A2 | 2000-11-08 | |||
| EP0241152A2 | 1987-10-14 | |||
| US5790539A | 1998-08-04 | |||
| US6069895A | 2000-05-30 | |||
| US5831980A | 1998-11-03 |
Other References:
NOTANI H ET AL: "An 8*8 ATM switch LSI with shared multi-buffer architecture", PROCEEDINGS OF THE SYMPOSIUM ON VLSI CIRCUITS. SEATTLE, JUNE 4 - 6, 1992, SYMPOSIUM ON VLSI CIRCUITS, NEW YORK, IEEE, US, 4 June 1992 (1992-06-04), pages 74 - 75, XP010064987, ISBN: 0-7803-0701-1
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