CHIP AND MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE

WIPO Patent Application WO/2024/045861

A1

Embodiments of the present application provide a chip and a manufacturing method therefor, and an electronic device. The problem that a gate control capability of a chip decreases along with miniaturization of a device size is solved. The chip comprises a substrate, a source, a drain, a first passage hole, a channel layer, a gate, and a gate dielectric layer; the side wall surface of the first passage hole is a recessed wall surface, and the channel layer is formed on the recessed wall surface. The recessed wall surface comprises the wall surface of a cavity formed by the side wall of the first passage hole being recessed in a direction parallel to the substrate, the formed wall surface of the cavity increases the formation position of the channel layer, so that the area of the channel layer is increased. Moreover, the cavity is located between the source and the drain, so that a partial surface of the source and a partial surface of the drain form the wall surface of the cavity, and then the area where the channel layer arranged on the wall surface of the cavity is in contact with the source and drain is increased, and a gate control capability is improved, thereby increasing the on-state current of the chip.

HUANG KAILIANG (CN)
JING WEILIANG (CN)
ZHANG WENQIANG (CN)
WANG ZHAOGUI (CN)
WANG ZHENGBO (CN)
LIAO HENG (CN)
KAR GOURI SANKAR (BE)
BANERJEE KAUSTUV (BE)

PCT/CN2023/104226

March 07, 2024

June 29, 2023

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HUAWEI TECH CO LTD (CN)

H01L29/786; H01L21/336; H01L29/417

CN111384156A	2020-07-07
CN113745346A	2021-12-03
CN112582464A	2021-03-30
KR101684798B1	2016-12-20
US20200006575A1	2020-01-02

BEIJING ZBSD PATENT & TRADEMARK AGENT LTD. (CN)

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