CHIP PACKAGING METHOD, AND PACKAGING STRUCTURE

WIPO Patent Application WO/2024/099219

A1

Provided in the present disclosure is a chip packaging method. The chip packaging method comprises: providing a substrate, wherein a first surface of the substrate has a plurality of pads; forming a pre-filling layer on the first surface of the substrate, wherein the pre-filling layer has a plurality of bump placement openings, and the plurality of pads are exposed from the plurality of bump placement openings, respectively; and mounting an electrical element on the pre-filling layer, wherein the electrical element has a plurality of solder bumps, and each solder bump of the electrical element is embedded into a corresponding bump placement opening among the plurality of bump placement openings, and is connected to a corresponding pad among the plurality of pads. In this way, the pre-filling layer acts as a blocking dam for the solder bumps of the electrical element, which is conducive to solving the problem of a short circuit in adjacent solder bumps of a chip, thus improving product yield. Further provided in the present disclosure is a packaging structure. In the packaging structure, a pre-filling layer is provided between a substrate and an electrical element.

WO/2020/027779	SIGNAL DISTRIBUTION FOR A QUANTUM COMPUTING SYSTEM
JP2004119863	CIRCUIT AND ITS PRODUCTION
JP2620355	Description: A method for manufacturing a semiconductor device and a manufacturing device.

LIU FEI (CN)

PCT/CN2023/129349

May 16, 2024

November 02, 2023

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SIPLP MICROELECTRONICS CHONGQING LTD (CN)

H01L21/48; H01L23/488

CN114499448A	2022-05-13
CN107564878A	2018-01-09
CN112038305A	2020-12-04
CN112349608A	2021-02-09
CN113471160A	2021-10-01
KR20080002501A	2008-01-04

BEIJING BESTIPR INTELLECTUAL PROPERTY LAW CORPORATION (CN)

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