Title:
CIRCUIT WITH INTERCONNECT TEST UNIT AND A METHOD OF TESTING INTERCONNECTS BETWEEN A FIRST AND A SECOND ELECTRONIC CIRCUIT
Document Type and Number:
WIPO Patent Application WO1999039218
Kind Code:
A3
Abstract:
The invention relates to interconnect testing of circuits. An electronic circuit (100) is described that has a plurality of input/output (I,O) nodes (130) for connecting the electronic circuit to a neighbouring electronic circuit via interconnects, a main unit (110) implementing an arbitrary normal mode function of the electronic circuit, and a test unit (120) for testing the interconnects. The test unit (120) in a test mode is operable as a low complexity memory via the I/O nodes (130). By writing to and or reading from the test unit (120) from a neighbouring circuit, the interconnects are tested. The invention particularly applies to complex memory devices, such as Synchronous Dynamic Random Access memories (SDRAM) and non-volatile memory like flash memory devices.
Inventors:
DE JONG FRANCISCUS G M (NL)
MURIS MATHIAS N M (NL)
RAAYMAKERS ROBERTUS M W (NL)
LOUSBERG GUILLAUME E A (NL)
MURIS MATHIAS N M (NL)
RAAYMAKERS ROBERTUS M W (NL)
LOUSBERG GUILLAUME E A (NL)
Application Number:
PCT/IB1999/000172
Publication Date:
September 23, 1999
Filing Date:
January 29, 1999
Export Citation:
Assignee:
KONINKL PHILIPS ELECTRONICS NV (NL)
PHILIPS SVENSKA AB (SE)
JONG FRANCISCUS G M DE (NL)
MURIS MATHIAS N M (NL)
RAAYMAKERS ROBERTUS M W (NL)
LOUSBERG GUILLAUME E A (NL)
PHILIPS SVENSKA AB (SE)
JONG FRANCISCUS G M DE (NL)
MURIS MATHIAS N M (NL)
RAAYMAKERS ROBERTUS M W (NL)
LOUSBERG GUILLAUME E A (NL)
International Classes:
G01R31/28; G01R31/3185; G06F11/22; G11C29/32; (IPC1-7): G01R31/28; G01R31/04
Foreign References:
| GB2278689A | 1994-12-07 | |||
| EP0588507A2 | 1994-03-23 |
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