[0001] This relates in general to electronic circuitry, and in particular to circuits and methods for transmitting signals.

BACKGROUND

[0002] Some communications techniques use "linear modulation using non-linear components" (LINC) modulation. LINC modulation is sometimes referred to as constant envelope out-phasing. LINC modulation transforms traditional Cartesian modulated RF signals with I and Q components to a combination of two constant envelope signals. The constant envelope signals are referred to as SI and S2 signals. The SI and S2 signals are phase modulated and can have any value in the phase domain.

[0003] Two issues make LINC modulation difficult at higher frequencies. The first issue is the calculations for achieving LINC modulations. More specifically, inverse cosine and inverse tangent functions are calculated, which is time consuming. In some embodiments, lookup tables are used for determining the inverse cosine and inverse tangent values, but the lookup tables occupy extensive memory, which is costly. The second issue is that the S 1 and S2 signals are phase modulated, which is difficult to achieve with sufficient accuracy at higher frequencies. SUMMARY

[0004] In described examples for generating quantized signals, a quantized phase domain related to quantized phases of an input signal is generated. Vectors that the input signal may occupy are calculated, based on the quantized phase domain. A first quantized phase of a first component of the input signal is generated per the quantized phase domain, and a second quantized phase of a second component of the input signal is generated per the quantized phase domain.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1 is a chart showing LINC modulation.

[0006] FIG. 2 is a chart showing a quantized phase domain.

[0007] FIG. 3 is the I/Q domain calculated, based on the quantized phase domain of FIG. 2.

[0008] FIG. 4 is an embodiment of a circuit for implementing processes of FIGS. 2 and 3. [0009] FIG. 5 is a flowchart showing the operation of the circuit of FIG. 4.

[0010] FIG. 6 is a chart showing an embodiment of asymmetrical multi-level out-phasing modulation.

[0011] FIG. 7 is a chart showing an embodiment of a quantized S 1/S2 phase domain with discrete power level outputs.

[0012] FIG. 8 is an embodiment of a circuit generating asymmetrical multi-level out-phasing modulated signals.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0013] In example embodiments, circuits and methods overcome shortfalls in LINC modulation, asymmetrical multi-level out-phasing (AMO) transmitters, and similar transmitters and modulation techniques. An S 1/S2 phase domain is quantized, and all of the possible I and Q vectors or values are determined, based on the quantized S 1/S2 domain. The I and Q vectors are discrete, because the S 1/S2 domain has been quantized. A quantizer quantizes the I and Q components of a complex input signal and fits them to the values in the I/Q domain that have been previously calculated. The SI and S2 components of the input signal are then readily determined in response to the quantized I and Q components of the input signal.

[0014] An example of LINC modulation in Cartesian coordinates is shown by the chart of FIG. 1. The chart is adapted onto the unit circle, in which the horizontal or x-axis is representative of the I component of a signal S(t), and the vertical or y-axis is representative of the Q component of the signal S(t). The value of the Q component is sometimes referred to as Q(t), and the value of the I component is sometimes referred to as I(t). In LINC modulation, the signal S(t) is represented by two components or values Sl(t) and S2(t), which are sometimes referred to herein simply as S I and S2. The magnitudes of S I and S2 are the same, but the phase angles 9(t) and cp(t) between the signals SI and S2 change to modulate the signal S(t). As shown in FIG. 1 , the value of S(t) as represented by Cartesian coordinates is given by equation (1) as follows:

S(t) = I (t) cos(<D _c t) + Q (t) sin(cL> _c t) Equation (1)

[0015] The term co _c is the frequency of the carrier of the signal S(t). The value of S(t) is also equal to the sum of S l(t) and S2(t), where S l(t) and S2(t) are shown by equations (2) and (3) as follows:

_{51 (t) =} Arnax _e ;(w _c t+< t)+e(t)) Equation (2) 52 ( _t ) = ^ _e i(w _c t+ ^< -0(t)) Equation (3)

[0016] The value of A(t), which is the magnitude of S(t), is calculated using the Pythagorean theorem, and A _max is maximum value of A(t) as shown by equation (4):

A(t) = V/ ² (t) + Q ² (t) Equation (4)

[0017] As described above, one issue with converting Cartesian signals to LINC modulated signals is that values of inverse cosine and inverse tangent are calculated to determine the phase angles. As shown in FIG. 1 , the value of 9(t) is calculated based on the inverse cosine as shown by equation (5), and the value of cp(t) is calculated based on the inverse tangent as shown by equation (6).

0 (t) = cos ^-1 (— ) Equation (5) φ (ί) = tan ^-1 Equation (6)

[0018] The calculations of inverse cosine and inverse tangent are complex. In some embodiments, they are not calculated, but are estimated using a lookup table. Lookup tables occupy relatively large amounts of memory, which is costly. Also, the phase modulator that generates the phases of S I and S2 is complex and is sensitive to timing errors. For example, a slight mismatch between the actual phase and the intended phase results in large linearity errors in the output signal. Also, physical distances and parasitic values between S I and S2 paths are difficult to match.

[0019] To overcome the problems described above, the phase domain of the S I and S2 signals is quantized as shown in FIG. 2. The signal S(t) is on a carrier clock, so the quantized phase domain is related to the different phases of the carrier clock. In the example of FIG. 2, the values of S I and S2 are limited to eight different phases of the carrier clock. Based on the quantized phase domain of FIG. 2, the I and Q domain is calculated as shown in FIG. 3. All of the possible values in the I and Q domain are calculated, based on all of the possible combinations of S 1 and S2 in the quantized phase domain of FIG. 2. Because the S 1/S2 phase domain is quantized, only a limited number of possible I and Q values exist, based on the S I and S2 combinations. By calculating all of the I and Q values, the complex calculations of inverse cosine and inverse tangent are unnecessary to perform during signal processing. The values of I and Q may be stored in a small lookup table that is readily accessed. Also, the sensitivity of the phase modulation between S 1 and S2 is eliminated. The I and Q components of a signal are processed together and quantized onto the chart of FIG. 3. Because the quantized S1/S2 domain was used for generating the I/Q domain, the SI and S2 values are readily determined, based on the quantized I and Q values. More specifically, the SI and S2 values are determined by the phase domain of FIG. 2, which was used for creating the I/Q domain of FIG. 3.

[0020] Having described the mathematical process of the modulation, a circuit for implementing the process will now be described. Reference is made to FIG. 4, which shows an embodiment of a block diagram of a circuit 200 for implementing processes described above. The circuit 200 includes an input 202, where complex components of an input signal are received on an I input 204 and a Q input 206. Both the I input 204 and the Q input 206 are connected to sampling circuits 208 and 210, where the complex components are upsampled by a frequency referred to as Fc. In some embodiments, the frequency Fc varies between 1.8 GHz to 2.5 GHz. The sampled signals are output to adders 214 and 216. As described in greater detail below, the adders 214 and 216 are components of noise shaping elements of the circuit 200.

[0021] The adders 214 and 216 output signals to filters 218 and 220, which provide for loop filtering of the sampled I and Q signals. The outputs of the filters 218 and 220 are output to (and received by) a quantizer 224, which is sometimes referred to as a complex quantizer 224. The quantizer 224 calculates the SI and S2 quantized phases from the I and Q quantized values. The quantizer 224 generates or has access to the quantized I and Q domain as shown in FIG. 3, which was calculated from the S1/S2 domain of FIG. 2. Because the I and Q components are quantized, only a limited number of I and Q vectors may be selected from the chart of FIG. 3. Based on these quantized values, the quantized values of SI and S2 are generated by the quantizer 224.

[0022] In the embodiment of FIG. 4, the quantizer 224 outputs voltages or signals representative of the SI and SI phases, which are shown as Sl_phase and S2_phase. Also, the quantizer outputs voltages representative of the quantized I and Q values. In some embodiments, the quantizer 224 outputs digital values representative of the SI and S2 phases. As described below, the SI and S2 phases are used for generating discrete phase modulated signals. The voltages representative of the quantized I and Q values are fed back to the adders 214 and 216, where they are subtracted from the sampled I and Q components that are output by the sampling circuits 208 and 210. The quantized I and Q values (in combination with the filters 218 and 220) provide for noise shaping of the signals that are output to (and received by) the quantizer 224. [0023] The outputs of the quantizer 224 are output to (and received by) a discrete phase modulator 230, which converts the digital values of the SI and SI phases to discrete SI and S2 phase modulated signals. A phase generator 232 generates discretely delayed pulses as shown by the timing diagram 233. The pulses generated by the pulse generator 232 are output to (and received by) multiplexers 234 and 236. The control signals for the multiplexers 234 and 236 are the voltages or digital values representative of the SI and S2 phases. The control signals determine which quantized phase is selected from the inputs of the multiplexers 234 and 236. The outputs of the multiplexers 234 and 236 are quantized SI and S2 components of phase modulated signals, which provide for quantized digital RF signals. The SI and S2 signals are output to a power amplifier 240. The SI and S2 signals are then combined by a conventional power combining circuit 242. In some embodiments, the power combining circuit 242 is a passive circuit.

[0024] The circuit 200 outputs a phase modulated signal, where the phases are discrete values. Accordingly, conventional phase modulation's complex calculations are avoided, so the circuit 200 is suitable for operating at high frequencies. The accuracy of the phase modulation is able to be increased by increasing the number of possible phases in the S1/S2 domain, which increases the number of possible quantized I and Q values. The circuit has many benefits over conventional modulators. For example, in some embodiments, the upsampling performed by the sampling circuits 208 and 210 operates at a high frequency, that noise is beyond the circuit's bandwidth. By quantizing the I and Q components simultaneously, they can be fit onto the I/Q domain of FIG. 3, which quickly yields the quantized phases from the S1/S2 phase domain of FIG. 2.

[0025] The operation of the circuit 200 and related techniques of generating quantized signals are discussed in connection with the flowchart 250 of FIG. 5. At step 252, a quantized phase domain related to quantized phases of an input signal is generated. In the embodiments described above, the phase domain corresponds to the chart of FIG. 2. Vectors that the input signal may occupy are calculated, based on the quantized phase domain at step 254. In the embodiments described above, the examples of the vectors are shown in FIG. 3. At step 256, a quantized phase of a first component of the input signal is generated per the quantized phase domain. A similar process is performed at step 258, where a quantized phase of a second component of the input signal is generated per the quantized phase domain. [0026] Portions of the above-described quantization may be applied to asymmetrical multi-level out-phasing (AMO) transmitters and modulation techniques using complex noise shaping and pulse width modulation (PMW). AMO transmission techniques decompose a complex signal into two components that are referred to as SI and S2. In some embodiments, the components are referred to as a 1 and a2. An example of the AMO technique is shown in the chart of FIG. 6, where I and Q components of a signal are decomposed to SI and S2 components. In AMO, the magnitudes of the SI and S2 components do not necessarily have the same magnitudes, which results in different voltage levels for the SI and S2 components.

[0027] As shown in FIG. 6, the complex signal has I and Q components and is defined by polar coordinates. An amplitude or magnitude A is calculated by the Pythagorean theorem as shown in equation (7), and the angle Θ is calculated by equation (8) as shown below.

A = ² + Q ² Equation (7)

Θ = tan ^"1 ^ Equation (8)

[0029] As shown in the above equations, AMO transmissions involve complex calculations. Also, the output level of an AMO transmitter changes to reflect the different amplitude values for SI and S2. In many conventional embodiments, the output level is changed by changing the voltage supply level to an output amplifier, which is inefficient. In some other conventional embodiments, the AMO is used with discrete pulse width modulation (PWM) of the radio frequency (RF) carrier. In these embodiments, the pulse widths are varied to change the output power, instead of changing the supply voltage to the output amplifier.

[0030] In the embodiments described herein, the output levels in the S1/S2 phase domain are quantized, which provides for discrete output power levels. The I/Q domain is then calculated, based on the discrete S1/S2 phase domain. The result is that the I/Q domain offers more resolution at lower power levels. In some embodiments, the multiple power levels are implemented by carrier pulse counting during a fixed period. For example, an RF carrier pulse may include pulses that are generated during a period of time. In some embodiments, sigma/delta modulation using a sigma/delta modulator (SDM) is used for the carrier pulse count transmission.

[0031] In some embodiments, the SDM operates at a clock frequency that is the carrier frequency divided by the number of power levels in the AMO. For an M-level AMO with a carrier frequency Fc, the clock frequency Fclk of the SDM will be Fc/M. The SDM uses the complex quantizer as described above to reduce the phase values of SI and S2 to discrete values. The SDM outputs have pre-quantized phase values and M possible amplitude values for the S 1 and S2 components. The modulation of the amplitude is implemented by changing the number RF clock pulses within one Fclk window. An output value of k (k=0...M) for an S1/S2 amplitude is translated as k carrier pulses placed in an Fclk window.

[0032] In this embodiment, the S1/S2 phase domain is quantized to also include discrete output power levels, as shown by the chart of FIG. 7. The embodiment of FIG. 7 has eight discrete phases and four discrete power levels, which yield a total of 32 possible discrete output levels. The discrete I/Q domain is then calculated, based on the discrete S1/S2 phase domain. The embodiment of the discrete S1/S2 phase domain of FIG. 7 yields 1024 discrete levels in the I/Q domain.

[0033] As briefly described above, the discrete power levels may be transmitted by a predetermined number of pulses or sidebands transmitted during a period. For example, a power level of PI may be conveyed by transmitting one pulse or sideband during the period, and a power level of P4 may be conveyed by transmitting four pulses or sidebands during the period.

[0034] Reference is made to a circuit 300 (FIG. 8) that implements the techniques of AMO transmission as described above. The circuit 300 has an input 302 that includes a first input 304 and a second input 306. The first input 304 is sometimes referred to as the I input 304, and the second input 306 is sometimes referred to as the Q input 306. The I input 304 receives the I component of a complex signal, and the Q input 306 receives the Q component of a complex signal. The I input 304 is connected to a sampling circuit 310 that upsamples the I component of the complex signal. Likewise, the Q input 306 is connected to a sampling circuit 312 that upsamples the Q component of the complex signal.

[0035] The output of the sampling circuit 310 is connected to an adder 314, and the output of the sampling circuit 312 is connected to an adder 316. As described below, error signals are output to (and received by) the adders 314 and 316 to subtract quantized I and Q error signals. The output of the adder 314 is connected to a filter 320, and the output of the adder 316 is connected to a filter 322. The filters 320 and 322 provide loop filtering and noise shaping. The filters 320 and 322 operate at a frequency Fclk, which is equal to Fc/4, where four possible power levels exist in the quantized S1/S2 domain. The frequency Fclk is the operating frequency of the sigma/delta modulator.

[0036] The outputs of the filters 320 and 322 are connected to a quantizer 324, which is sometimes referred to as a complex quantizer 324. The quantizer 324 generates the quantized S1/S2 phase domain of FIG. 5 and generates the quantized I and Q vectors, which may be generated by using a lookup table. The quantizer 324 fits the outputs of the filters 320 and 322 to the I/Q domain generated from the quantized S1/S2 domain of FIG. 7. The corresponding quantized SI and S2 values are then readily determined from the S1/S2 domain of FIG. 7. Because the circuit 300 is an AMO transmitter, the quantizer 324 outputs SI and S2 phase and amplitude values or voltages representing these values. Also, the quantizer 324 outputs voltages representative of the I and Q quantized values, which are fed back to the adders 314 and 316 for noise shaping.

[0037] The voltages representative of the SI and S2 phases are control signals for multiplexers 330 and 332. A phase generator 334 generates pulses that are output to (and received by) the multiplexers 330 and 332. In some embodiments, the phase generator 334 is identical to the phase generator 232 of FIG. 4. The phase generator 334 generates pulses that are delayed from each other by predetermined periods as shown by the chart 233 of FIG. 4. In the embodiment of FIG. 7, the phase generator 334 operates at the frequency Fc.

[0038] The phases selected by the multiplexers 330 and 332 are output to pulse count modulators 340 and 342. In some embodiments, the modulators 330 and 332 are RF pulse count modulators and operate similar to sigma/delta modulators. Each of the modulators 340 and 342 has an input from the quantizer 324. The modulator 340 has an input that is a voltage representative of the amplitude of the quantized SI component, and the modulator 342 has an input that is a voltage representative of the amplitude of the quantized S2 component. The modulators 340 and 342 generate pulses on the output signals that are representative of the SI and S2 amplitudes. In some embodiments, the number of pulses generated in a sampling period is indicative of the power level. For example one pulse generated during the sampling period is indicative of a first power level, and four pulses generated during the sampling period is indicative of a fourth power level. The pulse count modulators 340 and 342 may also increase the number of carriers to increase the power. In some embodiments, one carrier is representative of a first power level, and four carriers are representative of a fourth power level.

[0039] The signals generated by the modulators 340 and 342 are output to an amplifier 346 and then to a power combining circuit 350. The power levels of the SI and S2 components are in the modulated signal. Accordingly, unlike conventional AMO transmitters, the power levels of amplifier 346 do not have to change to reflect the power levels. The power combining circuit 350 combines the SI and S2 components for transmission. In some embodiments, the power combining circuit 350 is a passive circuit.

[0040] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.