Background Art Parallel concatenated convolutional codes, known as'Turbo'codes, have been disclosed in the paper'Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes (l)', Berrou, Glavieux and Thitimajshima, ICC'93 Geneva, May 23-26 1993, as well as in US 5446747. This type of code has attracted much attention in the digital transmission field because of its bit error rate performance close to the Shanron limit. The Turbo encoder as originally proposed consists of two recursive systematic convolutional coders. The two encoders receive the same information bits. cut the input of one of the encoders is connected to an interleaver so that the order of input bits is scrambled.

Parallel concatenated encoders using constituent codes other than convolutional codes have also been propose, for example in the article'Unveiling Turbo Codes: Some Results on Parallel Concatenated Coding Schemes'by Benedetto and NIontorsi, IEEE Transactions on Information Theory. Vol. 42. No. 2, March 1996, and in'Iterative Decoding of Turbo Codes and Other Concatenated Codes', a dissertation dated February 1996, by S. A. Barbulescu of the Institute of Telecommunications Research, University of South Australia.

However. the use of the interleaver in Turbo and related codes results in a long encoding delay, which has prevented their adoption in real time applications such as digital mobile telephony (see the article by Benedetto and Montorsi cited above).

Statement of the Invention According to the present invention, there is provided a parallel concatenated encoder which generates a sequence of data sets for transmission. Interleaved parity bits are not included in earlier data sets, which contain data bits and non-interleaved

parity bits. As a result, the delay incurred by interleaving the interleaved parity bits is not fully incurred in the output of the sequence of data sets as a whole; at the same time, uneven distribution of data bits and parity bits is avoided in a substantial part of the sequence.

In some embodiments of the invention, the interleaved parity bits have an index constraint substantially less than the size of the interleaver. This allows interleaved parity bits to be output before all of the data bits have been stored in the interleaver, further reducing the delay incurred by the encoder, without significantly increasing the bit error rate over a transmission channel.

Brief Description of the Drawings Specific embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram of a satellite communications system: Figure 2 is a schematic diagram of an earth station in the system of Figure 1; Figure 3 is a schematic diagram of a turbo encoder in the earth station of Figure 2 ; Figure 4 shows the features of the buffer of Figure 3; Figure 5 is a diagram of the modulation scheme implemented by the modulator of the earth stations; Figure 6 is a diagram of the transmission frame format used by the earth stations ; Figure 7 is a diagram of the delay incurred in transmission of a frame over the satellite link in a conventional output format; Figure 8 is a diagram of the order of transmission of bits from the encoder in a first embodiment of the present invention; Figure 9 is a diagram of the order of transmission of bits from the encoder in a second embodiment of the present invention;

Figure 10 is a diagram of the order of transmission of bits from the encoder in a third embodiment of the present invention; and Figure 11 is a diagram of the order of transmission of bits from the encoder in a fourth embodiment of the present invention.

Modes for Carrving Out the Invention As shown in Figure 1, mobile terminal equipment 4 is connected to a mobile earth station (MES) 6. The mobile terminal equipment 4 may comprise telephone equipment, facsimile equipment or data terminal equipment, and may include interface equipment for allowing telephone, facsimile or data terminals designed for connection to other types of network to be connected to the satellite network.

Examples of such interface equipment are described in GB 2286739, US 5587810, GB 2300540. and WO 97/00561. The mobile terminal equipment 4 sends digital data to the MES 6 for RF modulation and transmission to a satellite 8, and the MES 6 receives and demodulates digital data from the satellite 8, the demodulated data then being sent to the mobile terminal equipment 4.

The satellite 8 carries a transponder which receives modulated signals, converts them to an intermediate frequency, amplifies them and retransmits them at a different frequency from the received frequency. The satellite 8 thereby links the MES 6 to a land earth station (LES) 10, so that signals transmitted by the MES 6 are received by the LES 10 and vice versa, via the satellite 8.

The LES 10 is connected to a network interface 12 for providing an interface to a network 14, in this case a PSTN. A call is thereby connected over the network 14 to fixed terminal equipment 16, which comprises telephone, facsimile or data terminal equipment compatible with the mobile terminal equipment 4.

Figure 2 shows the relevant functional sections of both the MES 6 and the LES 10 in more detail. The functions of the MES 6 and the LES 10 are distinct in other respects. but for convenience the same diagram and reference numerals are used for the relevant sections of both.

Digital data received from the mobile terminal equipment 4 or network interface 12 is encoded by an encoder 20 and then modulated by a modulator 24. The modulated output is transmitted by an antenna assembly 28. Signals received from the antenna assembly 28 are demodulated by a demodulator 30 to generate digital data which is decoded by a decoder 34. The output of the decoder 34 is connected to the mobile terminal equipment 4. The operation of the functional sections is controlled by a controller 36.

The encoder 20 is a Turbo encoder of the type shown in Figure 3. Data bits dk are input to a first encoder ENC1, and to an interleaver 21, the output of which is connected to a second encoder ENC2. Each encoder ENC1 and ENC2 is a recursive convolutional coder comprising four intermediate binary stores D1 to D4, and binary adders or exclusive-OR gates. With each cycle, the contents of each of the binary stores Dl to D3 is shifted to binary stores D2 to D4 respectively, while the new <BR> <BR> <BR> <BR> contents of D1 are derived from the previous contents of D2 to D4. The output Pk from the first encoder and the output qk from the second encoder are derived from the contents of the binary stores D1, D2 and D4 and from the input to the binary store D1.

The data bits dk, the non-interleaved parity bits Pk and the interleaved parity <BR> <BR> <BR> <BR> bits qk are output to a buffer 23 from which sets of bits (ul, u"U3, U4) are output in parallel in accordance with a puncturing format, examples of which are described below.

As shown in Figure 4, the buffer 23 comprises memory stores Sd, Sp and Sq for the data bits d, non-interleaved parity bits p and interleaved parity bits q respectively. Data and parity bits are read out of the memory stores S from addresses indicated by first and second pointers Pdl, Pd2, Ppl, Pp2, Pql, Pq2 for each of the memory stores Sd, Sp and Sq respectively and output as a selected one of the output <BR> <BR> <BR> <BR> bits ul, U2, U3, U4 determined by a multiplexer 25. The sequence of addresses from which the data and parity bits are read out and the sequence of settings of the multiplexer together determine the transmission format of the data and parity bits and the puncturing scheme of the parity bits, not all of which are transmitted. The

arrangement shown in Figures 3 and 4 is a functional representation of the turbo encoder and may be implemented entirely in a suitably programme digital signal processor (DSP).

In a conventional format, the outputs of the encoder 20 are rate half punctured and modulated as follows. At each clock cycle, the systematic data bit dk is selected as output together with an alternating one of the parity bits Pk, qk The parity bit which is not selected is discarded. The output data bits and parity bits for each pair of clock cycles are modulated as one symbol in a 16QAM (16 quadrature amplitude modulation) scheme.

The conventional format is represented in Table 1 below.

Table 1 Cycle 1 4 data dk d, d2 d3 d4 parity Pk P3 parity qk q2 q4 16QAM Symbol (dl, Pl, d2, p3, d4, q4) I Each symbol is formed from the four bits (ul, u"U3, U4) with the bits ul, u2<BR> <BR> modulating the I (amplitude) component and the bits U3, u4 modulating the Q (phase) component such that: The modulation scheme, as shown in Figure 5, is square 16QAM, although a circular 16QAM scheme may be used. The data bits Ut, U3 are the most protected in the 16QAM symbol.

The symbols are transmitted in a frame format as shown in Figure 6. Data is transmitted in a single channel per carrier (SCPC) channel format. The start of a data

sequence is indicated by a preamble P and a unique word UW to aid acquisition of the channel. The data is then transmitted in frames F, to F each consisting of 16QAM symbols interspersed with PSAM (pilot symbol assisted modulation) blocks PS, to allow measurement of fading and noise variance, so as to assist in decoding.

At the end of each frame is a framing bit pattern FB. Encoded in the symbols of each frame are two turbo-coded sub-frames C, and C2 corresponding to two unencoded sub-frames S, and S2. The end of the data sequence is indicated bv an end of data signal EOD.

The size of the interleaver 21 of the encoder 20 is equal to that of the subframes S, and S2. In one example, the interleaver 21 is a random interleaver in which an entire block is loaded into the interleaver 21 and the contents are then output in a pseudo-random order. In this case, the entire contents of one of the subframes S, or S2 are loaded into the interleaver 21 before the parity bits qk are output. Hence, the delay incurred by the encoder 20 is at least N, where N is the time taken to receive the number of bits in one of the subframes S, or S,. The delay is shown graphically in Figure 7, with time on the horizontal axis. In the encoder output, the different bits (ul, u2, u3, u4) are indicated on the vertical axis.

In accordance with embodiments of the present invention, the delay incurred by the encoder 20 is reduced to a fraction of the delay N in the scheme described above, by rearranging the order of transmission of the data bits d and the parity bits p and q. Each embodiment is shown using a rate half turbo code, although other rates may be used.

In a first embodiment, as shown in Figure 7, the parity bits p are output in the first half of a subframe C and the interleaved parity bits q are output in the second half of the subframe C. Note that the interleaved parity bits q are only output once all of the data bits d have been received, but the delay involved is reduced to N/2 because two interleaved parity bits q are transmitted per symbol, since all the parity bits p have already been transmitted.

In a second embodiment shown in Figure 8, all of the data bits d and the parity bits p are transmitted before the interleaved parity bits q. During the first

quarter of the subframe C, only the data bits d are transmitted; during the middle half of the subframe C, data bits and parity bits p are transmitted; during the final quarter of the subframe C, only the interleaved parity bits q are transmitted. Hence, the delay is reduced to N/4 because four interleaved parity bits q are transmitted per symbol.

However, half of the data bits d in the first quarter of the subframe C are transmitted <BR> <BR> <BR> <BR> as the less protected bits (U2, U4) of the 16QAM symbols, leading to an increase in bit error rate relative to the first embodiment. Moreover, since the distribution of data bits d and parity bits p, q is uneven throughout the subframe C, the format is particularly susceptible in fading channels with a fade rate comparable to the subframe rate. In such a case, the data bits in the first quarter of the subframe C may repeatedly coincide with the fading, giving a high bit error rate.

In the third and fourth embodiments described below, the interleaver 21 is subject to an index constraint such that: max- i=O... N-l where i is the order of a data bit input to the interleaver 21 and z (i) is the corresponding output order. As a result, it is possible to begin output of the interleaved parity bits after only N/2 data bits have been input into the interleaver 21.

The index constraint has a small effect on the bit error rate performance, but gives greater flexibility in the format of the subframe C, as shown below.

In a third embodiment of the present invention, as shown in Figure 9, the data bits d are evenly distributed throughout the subframe C and always occupy the two most protected bit positions of the 16QAM symbol. In the first quarter of the subframe C, the first half of the non-interleaved data bits p occupy 2 bits per symbol; in the middle half, the second half of the non-interleaved parity bits p and the first half of the interleaved parity bits q each occupy one bit per symbol; in the final quarter, the second half of the interleaved parity bits q occupy two bits per symbol.

The resultant delay is N/4 bits, as in the second embodiment, but the problems of less protected data bits d and uneven distribution of data bits and parity bits are avoided.

In a fourth embodiment of the present invention, as shown in Figure 10, the effective delay is reduced to N/8, at the expense of the disadvantages of the second embodiment. In the first eighth of the subframe C, all four bit positions of the symbol are occupied by data bits d. In the next quarter, the two most protected bit positions are occupied by data bits d, while the two less protected bit positions are occupied by the non-interleaved parity bits p. In the next half, the two more protected bit positions are also occupied by data bits d, while one each of the less protected bit positions are occupied by the non-interleaved parity bits p and the interleaved parity bits q. In the final eighth of the subframe C, all of the bit positions are occupied by the interleaved parity bits q.

In the decoder 34, the bits are demodulated and a probability is estimated for each bit. The demodulated bits are separated into data bits d, non-interleaved parity bits p and interleaved parity bits q according to the format used for transmission. The bits are then decoded using a MAP decoder, of the type known from example from 'Implementation and performance of a serial MAP decoder for use in an iterative turbo decoder'. S. S. Pietrobon, IEEE Int. Symp. Inform. Theory. Whistler, British Columbia, Canada, Sep. 1995.

Modifications of the above embodiments may be envisaaed within the scope of the present invention. For example, alternative modulation schemes may be used, such as 8PSK (8 phase shift keying). Alternative rate codes may be produced, by using different puncturing rates. Although recursive convolutional codes are preferred as the constituent codes of the encoder 20, other constituent codes such as block codes may be used. The data bits d may be pre-coded before being input to the encoder 20, and/or further encoded after being output from the buffer 21.

The above embodiments are provided purely by way of example, and further modifications may be envisaged without departing from the scope of the appended claims.