Title:
COMBINED FORMAL AND NON-FORMAL CIRCUIT VERIFICATION
Document Type and Number:
WIPO Patent Application WO/2004/104871
Kind Code:
A2
Abstract:
Integrated proof flow methods and apparatuses are discussed. Integrated proof flow refers to attempting both formal verification and nonformal verification. A coverage metric can be changed by both attempting formal verification and by attempting nonformal verification. Some embodiments of the present invention provide proof flow methods that integrate verification and nonformal verification (e.g., bounded verification, multi-point proof, and/or vector-based simulation) to prove one or more properties in a circuit design.
Inventors:
CHEN KUANG-CHIEN (US)
WANG BOW-YAW (CN)
WANG BOW-YAW (CN)
Application Number:
PCT/US2004/015093
Publication Date:
December 02, 2004
Filing Date:
May 14, 2004
Export Citation:
Assignee:
CADENCE DESIGN SYSTEMS INC (US)
CHEN KUANG-CHIEN (US)
WANG BOW-YAW (CN)
CHEN KUANG-CHIEN (US)
WANG BOW-YAW (CN)
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| WO2001088765A2 | 2001-11-22 |
Foreign References:
| US6553514B1 | 2003-04-22 |
Other References:
AZZONI P ET AL: "An error simulation based approach to measure error coverage of formal properties" GLSVLSI '02. PROCEEDINGS OF THE 12TH ACM GREAT LAKES SYMPOSIUM ON VLSI ACM NEW YORK, NY, USA, 2002, pages 53-58, XP002336669 ISBN: 1-58113-462-2
YUAN LU ET AL: "A semi-formal verification methodology" ASIC, 2001. PROCEEDINGS. 4TH INTERNATIONAL CONFERENCE ON OCT. 23-25, 2001, PISCATAWAY, NJ, USA,IEEE, 23 October 2001 (2001-10-23), pages 33-37, XP010576703 ISBN: 0-7803-6677-8
EMMITT J: "Open Verification Library Aids Formal Verification and Simulation Methodology" TECHONLINE, [Online] February 2001 (2001-02), pages 1-6, XP002336670 Retrieved from the Internet: URL:http://www.techonline.com/community/ed _resource/feature_article/12462?print> [retrieved on 2005-07-19]
FERRANDI F ET AL: "Functional test generation for behaviorally sequential models" DESIGN, AUTOMATION AND TEST IN EUROPE, 2001. CONFERENCE AND EXHIBITION 2001. PROCEEDINGS 13-16 MARCH 2001, PISCATAWAY, NJ, USA,IEEE, 13 March 2001 (2001-03-13), pages 403-410, XP010538223 ISBN: 0-7695-0993-2
YUAN LU ET AL: "A semi-formal verification methodology" ASIC, 2001. PROCEEDINGS. 4TH INTERNATIONAL CONFERENCE ON OCT. 23-25, 2001, PISCATAWAY, NJ, USA,IEEE, 23 October 2001 (2001-10-23), pages 33-37, XP010576703 ISBN: 0-7803-6677-8
EMMITT J: "Open Verification Library Aids Formal Verification and Simulation Methodology" TECHONLINE, [Online] February 2001 (2001-02), pages 1-6, XP002336670 Retrieved from the Internet: URL:http://www.techonline.com/community/ed _resource/feature_article/12462?print> [retrieved on 2005-07-19]
FERRANDI F ET AL: "Functional test generation for behaviorally sequential models" DESIGN, AUTOMATION AND TEST IN EUROPE, 2001. CONFERENCE AND EXHIBITION 2001. PROCEEDINGS 13-16 MARCH 2001, PISCATAWAY, NJ, USA,IEEE, 13 March 2001 (2001-03-13), pages 403-410, XP010538223 ISBN: 0-7695-0993-2
Attorney, Agent or Firm:
Mei, Peter C. (Three Embarcadero Center Suite 180, San Francisco CA, US)
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