[0001] This disclosure relates generally to electronic circuit systems, and more specifically to current-limiting in an amplifier system.

BACKGROUND

[0002] Amplifier systems can be implemented for a variety of electronic circuit applications to increase an input signal's amplitude in generating an output signal. For example, current amplifiers can generate an output current whose amplitude is greater than a respective input current's amplitude. Similarly, voltage amplifiers can generate an output voltage whose amplitude is greater than a respective input voltage's amplitude. One example application of an amplifier system is servo control for the motion of mechanical components, such as a dual-stage actuator in a hard-disk drive (HDD). For example, the input signal can be provided for positioning control of a head to read and write data, so the amplifier can provide the output signal to move the head.

SUMMARY

[0003] In described examples, an amplifier system includes a gain stage configured to conduct a gain current in response to an input voltage. The system also includes a current limit stage coupled to the gain stage and configured to source and/or sink the gain current and to define a limit amplitude of the gain current during a current limit condition. The system further includes an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.

[0004] In another embodiment, a gain stage includes multiple transistors configured to conduct at least one of a sinking current and a sourcing current in response to an input voltage. The system also includes at least one current limit stage, which includes a current mirror configured to provide the at least one of the sinking current and the sourcing current and to define a limit amplitude of the at least one of the sinking current and the sourcing current during a current limit condition. The system further includes an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the at least one of the sinking current and the sourcing current to provide an output voltage at the output node, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.

[0005] Another embodiment includes a hard-disk drive (HDD) system. The system includes a magnetic disk configured to store data and a spindle motor configured to control rotation of the magnetic disk. The system also includes a head configured to write data to and read data from the magnetic disk. The system further includes a dual-stage actuator configured to cooperate with a voice coil motor to position the head with respect to the magnetic disk in response to an output voltage generated by an amplifier system. The amplifier system includes a gain stage configured to conduct a gain current in response to an input voltage. The amplifier system also includes a current limit stage coupled to the gain stage, and which is configured to source and/or sink the gain current and to define a limit amplitude of the gain current during a current limit condition. The amplifier system further includes an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current to provide an output voltage at the output node, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 illustrates an example of an amplifier system.

[0007] FIG. 2 illustrates an example of an amplifier circuit.

[0008] FIG. 3 illustrates an example of a hard-disk drive (HDD) system.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0009] In one example, the amplifier system can be a voltage amplifier configured to generate an output voltage that is an amplified version of an input voltage. For example, the input voltage can be a differential voltage that is provided via feedback. The amplifier system can include a gain stage, a current limit stage, and an output stage. The gain stage can be configured to conduct a gain current, such as a sinking current or a sourcing current, based on the input voltage. For example, the input voltage can activate one or more transistors in the gain stage to conduct the gain current. The output stage is coupled to the gain stage, and is configured to generate an output current that is based on the gain current, and to provide an output voltage based on the output current.

[0010] The current limit stage can be configured to define a limit amplitude of the gain current associated with a current limit condition, with the current limit condition corresponding to a current amplitude limit associated with the output current. For example, the current limit stage can include a current limit stage configured to sink the gain current and/or source the gain current based on a difference between the two voltages that constitute the differential input voltage. For example, the gain stage can include sets of cross-coupled transistors that, during a current limit condition, are mutually exclusively activated to conduct the sinking gain current or the sourcing gain current, respectively. The current limit stage is configured to generate the gain current (e.g., sinking and/or sourcing current), and can define a limit amplitude associated with the gain current via a current mirror, such that the output current has an amplitude limit that is proportional to the defined limit of the gain current.

[0011] FIG. 1 illustrates an example of an amplifier system 10. The amplifier system 10 can correspond to a voltage amplifier, such as can be implemented to provide an output voltage VOU _T that has an increased amplitude relative to an input voltage Vm. For example, the amplifier system 10 can be implemented in a variety of electronics applications, such as for a dual-stage actuator driver in a hard-disk drive (HDD) system.

[0012] The amplifier system 10 includes a reference stage 12 that is configured to set at least one predetermined reference voltage based on a high-voltage rail and a low-voltage rail, shown in FIG. 1 as a voltage V _DD and ground, respectively. For example, the voltage V _DD can be approximately 5 volts. The amplifier system 10 also includes at least one gain stage 14 that includes multiple transistors 16. The gain stage(s) 14 is/are configured to conduct a gain current that is generated based on the input voltage Vm. For example, the transistors 16 can be activated based on the input voltage and the reference voltage(s) to conduct the gain current. Also, for example, the transistors 16 can include two pairs of cross-coupled transistors as part of a first of the gain stage(s) 14, with: a first transistor of each pair being controlled by one of the one or more reference voltages; and a second transistor of each pair being controlled based on the input voltage V _IN . For example, the input voltage V _IN can be a differential input voltage V _IN having a first voltage and a second voltage, which are provided via feedback.

[0013] A first of the gain stage(s) 14 can be configured to conduct the gain current as a sinking gain current or a sourcing gain current based on the input voltage V _IN - For example, the first of the gain stage(s) 14 can provide the gain current as a sourcing gain current based on a positive difference between the differential voltages of the input voltage V _I or as a sinking gain current based on a negative difference between the differential voltages of the input voltage Vm. Also, for example, the first of the gain stage(s) 14 can be configured to mutually exclusively activate a given one pair of the cross-coupled transistors of the transistors 16 in response to a difference between the first and second voltages of the differential input voltage VIN exceeding a predetermined threshold.

[0014] The amplifier system 10 also includes an output stage 18 that is configured to generate an output current based on the gain current. For example, the output stage 18 can be coupled to a second of the gain stage(s) 14 that includes at least one current mirror, which can be configured to conduct the gain current from the first transistor in each of the pairs of cross-coupled transistors in the transistors 16, such that the mirrored gain current can control at least one transistor in the output stage 18. The output stage 18 can include a source-follower arrangement of transistors that are controlled by the mirrored gain current, such that the source-follower arrangement of transistors can be configured to conduct the output current through an output node 20 (such as sourced by a voltage V _P or sunk to a voltage V _N , respectively) to provide the output voltage VOUT corresponding to an increased magnitude of the input voltage VIN- For example, the voltage Vp can have an amplitude that is greater than the amplitude of the voltage VDD, such as approximately 17.5V. For example, the output current can be proportional to the gain current based on respective gate-widths of the transistors between the transistors in the gain stage(s) 14 and the source-follower arrangement of transistors in the output stage 18. Additionally, the source-follower arrangement of the transistors in the output stage 18 can provide a low output impedance with respect to the output node 20, such as can be required in certain voltage amplifier applications.

[0015] In the example of FIG. 1 , the amplifier system 10 further includes at least one current limit stage 22 that is configured to limit the amplitude of the output current during a current limit condition to substantially prevent damage to the amplifier system 10 or associated electronics. In a current limit condition, the output current flows from the amplifier system 10 via the output node 20, or into the amplifier system 10 via the output node 20, via the output stage 18 at a maximum amplitude, such as in response to a short-circuit or a very low resistance current path from the output node 20 to a low-voltage rail (e.g., ground). The current limit stage(s) 22 can include a current mirror that is configured to provide the gain current that the gain stage(s) 14 conduct(s), and to define an amplitude limit of the gain current, which can thus limit the amplitude of the output current based on the proportionality of the output current with respect to the gain current.

[0016] For example, the current limit stage(s) 22 can include a sourcing current limit stage and a sinking current limit stage that are respectively configured to conduct the gain current via the gain stage(s) 14. Each of the sourcing and sinking current limit stage(s) 22 can include a current mirror that conducts a predetermined current that can define a maximum amplitude of the gain current. Therefore, because the output current is proportional to the gain current, the output current can have a maximum amplitude that is proportional to the amplitude limit of the gain current, as defined by the current limit stage(s) 22. Accordingly, in response to a current limit condition, the output current can have a maximum amplitude that is set by the current limit stage(s) 22.

[0017] FIG. 2 illustrates an example of an amplifier circuit 50. The amplifier circuit 50 can correspond to a voltage amplifier to provide an output voltage VOU _T that has an increased amplitude relative to a differential input voltage, which is shown in FIG. 2 as a first voltage V _{IN N} and a second voltage V _IN _p. For example, the amplifier circuit 50 can be implemented in a dual-stage actuator driver in an HDD system. Also, for example, the amplifier circuit 50 can correspond to the amplifier system 10 in FIG. 1. Accordingly, FIG. 1 is referenced by the following description of FIG. 2.

[0018] In the example of FIG. 2, the first input voltage Vi _{N N} ^an d the second input voltage V _IN p are provided to respective gates of p-channel metal-oxide semiconductor field-effect transistors ("P-FETs") Pi and P ₂ . Pi interconnects a current source 52 and a first control node 54, and P ₂ interconnects the current source 52 and a second control node 56. The current source 52 is configured to conduct a current Ii from the voltage V _DD - The input voltages V _{IN P} and V _{IN N} can be approximately equal during a steady-state normal operating condition of the amplifier circuit 50, such as based on feedback to establish the normal operating condition. In another example, the amplifier circuit 50 can be configured as an inverting amplifier, such that the input voltage V _{IN P} can be substantially fixed at a predetermined amplitude, such as less than 1 volt (e.g., approximately 900m V), and the input voltage V _{IN N} can have an amplitude that varies around the amplitude of the input voltage V _I N _P (e.g., +/- 700mV of the input V _I N _P ). The input voltages V _{IN N} and V _{IN P} can operate Pi and P ₂ in the saturation region to provide a voltage Vswi on the first control node 54 and a voltage Vsw ₂ on the second control node 56, respectively. [0019] The amplifier circuit 50 includes a reference stage 58, which includes an n-channel metal-oxide semiconductor field-effect transistor ("N-FET") Ni and a P-FET P ₃ that are each diode-connected in series and interconnect a first reference node 60 and a second reference node 62. A current source 64 provides a reference current I _REF from the voltage V _DD through Ni and P ₃ , and through a diode-connected N-FET N ₂ that is coupled to P ₃ and to a diode-connected N-FET N ₃ that is coupled to N ₂ and to ground. Based on the diode-connection of Ni, P ₃ , N ₂ and N ₃ between the voltage V _DD and a low-voltage rail (shown in FIG. 2 as ground), the reference nodes 60 and 62 have respective reference voltages V _REFI and V _REF2 that are substantially constant.

[0020] Also, the gate of N ₂ is coupled to respective gates of an N-FET N ₄ and an N-FET N ₅ , and the gate of N ₃ is coupled to respective gates of an N-FET N ₆ and an N-FET N ₇ . Therefore, N ₆ , and N ₇ are arranged as current mirrors with respect to N ₃ . N ₂ , N ₄ and N ₅ are arranged as cascode stages with respect to N ₃ , N ₆ and N ₇ , respectively. The first control node 54 interconnects the source of N ₄ and the drain of N ₆ , and the second control node 56 interconnects the source of N ₅ and the drain of N ₇ . The drain of N ₄ is coupled to a diode-connected P-FET P ₄ having a common gate connection and a common source connection (e.g., at the voltage V _DD ) with a P-FET P5, such that P5 is arranged as a current mirror with respect to P ₄ . As a result, the reference current I _REF is mirrored through P ₄ and N ₄ as a current I _M1 and through N ₅ as a current I _M2 , such that the currents I _M1 and I _M2 are mirrored versions of the current I _REF minus one half of the current Ii in normal operating conditions. However, a relative magnitude of the voltages Vswi and Vsw ₂ at the respective control nodes 54 and 56 can control activation of N ₄ and N ₅ , based on the coupling of the respective control nodes 54 and 56 to the sources of N ₄ and N ₅ . Thus, the relative amplitudes of the currents I _MI and I _M2 can be controlled based on the relative amplitudes of the respective voltages Vswi and Vsw2-

[0021] The amplifier circuit 50 also includes a first gain stage 66. The first gain stage 66 includes a diode-connected N-FET Ns having a common gate connection at a first bias node 68 with an N-FET N ₉ , and includes a diode-connected P-FET P ₆ having a common gate connection at a second bias node 70 with a P-FET P ₇ . Therefore, N ₉ and P ₇ operate as a current mirror with respect to Ng and P ₆ . In the example of FIG. 2, the first bias node 68 is also coupled to the drain of P ₅ and has a voltage V _BI , and the second bias node 70 is also coupled to the drain of N ₅ and has a voltage V _B2 . As described in greater detail herein, the voltages V _B i and V _B2 are controlled by the currents I _MI and I _M 2 via the voltages Vswi and Vsw2, and are thus controlled by the differential input voltage V _IN _p and Vi _N _ _Ν · Also, the first gain stage 66 includes an N-FET N ₁₀ and a P-FET P ₈ that are controlled by the reference voltages V _REFI and V _REF 2, respectively, and are thus arranged as a current mirror with respect to Ni and P ₃ in the reference stage 58. Ng is coupled via a common source connection to P ₆ at a node 72. The sources of Ng, N ₁₀ , P ₇ and Pg are all coupled at a node 74 having a voltage VCO _M - Therefore, Ng, N ₁₀ , P ₇ and Pg are arranged as cross-coupled pairs of transistors, with Ng and Pg constituting a first pair of the cross-coupled transistors, and with N ₁₀ and P ₇ constituting a second pair of the cross-coupled transistors, as described in greater detail herein.

[0022] The amplifier circuit 50 also includes a first current limit stage 76 and a second current limit stage 78. The first current limit stage 76 is configured to generate a gain current as a sourcing current IS _R C, which is provided to the first gain stage 66 (by being provided to a drain of Ng). In the example of FIG. 2, the first current limit stage 76 includes a diode-connected P-FET P ₉ having a common gate connection with a P-FET P ₁₀ and having a common source connection to the voltage V _DD - Therefore, Pg and P ₁₀ cooperate as a current mirror. The first current limit stage 76 also includes a current source 80 that is configured to conduct a substantially constant current I _L1 from the voltage V _DD through Pg to ground. Therefore, the substantially constant current In can define a maximum amplitude for the current IS _R C that is based on the amplitude of the current I _L1 and based on relative gate widths of the transistors in the current path of the current I _SRC (e.g., including P ₁₀ ).

[0023] Similarly, the second current limit stage 78 is configured to generate the gain current as a sinking current IS _NK that is provided from the first gain stage 66 (by being provided from a drain of P ₇ ). In the example of FIG. 2, the second current limit stage 78 includes a diode-connected N-FET Nn having a common gate connection with an N-FET N ₁₂ and a common source connection to ground. Therefore, Nn and N ₁₂ cooperate as a current mirror. The second current limit stage 78 also includes a current source 82 that is configured to conduct a substantially constant current I _L2 from the voltage V _DD through Nn to ground. Therefore, the substantially constant current I _L2 can define a maximum amplitude for the current IS _NK that is based on the amplitude of the current I _L2 and based on relative gate widths of the transistors in the current path of the current IS _NK (e.g., including N ₁₂ ).

[0024] The amplifier circuit 50 also includes a second gain stage 84 and an output stage 86 that are coupled via an output control node 88. The second gain stage 84 is coupled to the first gain stage 66 via: (a) a capacitor Ci that interconnects the node 72 and the output control node 88; and (b) N ₁₀ and P ₈ . In the example of FIG. 2, the second gain stage 84 includes a diode-connected N-FET N ₁₃ having a common gate connection with an N-FET N ₁₄ at a drain of P ₈ in the first gain stage 66, and having a common source connection to the voltage V _N (e.g., a negative voltage, such as approximately - 17.5 volts). Similarly, the second gain stage 84 includes a diode-connected P-FET Pn having a common gate connection with a P-FET P ₁₂ at a drain of N ₁₀ in the first gain stage 66, and having a common source connection to the voltage Vp (e.g., a voltage that is equal and opposite the voltage V _N , such as approximately 17.5 volts). The drains of N ₁₄ and P ₁₂ are coupled to the output control node 88. Therefore, N ₁₃ , N ₁₄ , Pn and P ₁₂ each respectively cooperate as current mirrors that are configured to conduct the gain current through the first gain stage 66 and mirror the gain current through the output control node 88. For example, N ₁₄ and P ₁₂ can have a larger gate width relative to N ₁₃ and Pn, respectively, such as based on a fixed proportion (e.g., a gate width that is twice the gate width of N ₁₃ and Pn, respectively).

[0025] The output stage 86 includes an N-FET N ₁₅ and an N-FET N ₁₆ that are configured in a source-follower arrangement, and thus can provide a low output impedance with respect to an associated output node 90. In the example of FIG. 2, N ₁₅ is diode-connected at the output control node 88, with N ₁₅ and N ₁₆ having a common gate and a common source to provide a current mirror configuration. The sources of N ₁₅ and N ₁₆ are coupled to the output node 90 having the output voltage VOU _T , and the drain of N ₁₆ is coupled to the voltage Vp. The output stage 86 also includes an N-FET N ₁₇ , which has a gate coupled to the gates of N ₁₃ and N ₁₄ in the second gain stage 84, and which interconnects the output node 90 at a drain and the voltage V _N at a source. Accordingly, N ₁₇ is arranged as a current mirror with respect to N ₁₃ . N ₁₆ and N ₁₇ are therefore configured to conduct the output current based on the gain current that is conducted through the first gain stage 66 and the second gain stage 84. For example, N ₁₆ can have a gate width that is significantly greater than the gate width of N ₁₅ (e.g., approximately twenty-five times the gate width of N ₁₅ ). Similarly, N ₁₇ can have a gate width that is significantly greater than the gate width of Ni ₃ (e.g., approximately fifty times the gate width of N ₁₃ ). Further, in the example of FIG. 2, a diode Di interconnects the source and the drain of N ₁₅ from anode to cathode, respectively. For example, the diode Dl can be configured as a parasitic diode with respect to N ₁₅ . The diode Di is configured to conduct the output current from the output node 90, as described in greater detail herein.

[0026] In the example of FIG. 2, additional currents are shown in the amplifier circuit 50, particularly in the first gain stage 66, the second gain stage 84, and the output stage 86. The currents described hereinafter have current flow directions that are based on positive amplitudes. Therefore, as described herein, a negative amplitude of the currents indicates a current flow in the opposite direction of that shown in FIG. 2.

[0027] As a first example, the input voltages Vi _N p and Vi _{N N} ^can be approximately equal (e.g., each having an amplitude of approximately 900 mV). In response, with reference to the example of FIG. 2, the voltages Vswi and Vsw ₂ can be approximately equal to provide amplitudes of the currents I _MI and I _M2 that are likewise approximately equal. Therefore, the first and second bias voltages V _BI and V _B2 can be approximately equal to the voltages V _REFI and V _REF 2, respectively, and the voltage at the node 72 can be approximately equal to the voltage VCO _M , to provide for saturation region activation of Ng and P ₇ . Therefore, based on the amplitude of the voltage VCO _M at the node 74 at the sources of Nio and Ps, Nio and Ps are also each activated in the saturation region.

[0028] In response to the activation of Ng, Nio, P7 and Pg in the saturation region: (a) the current IS _R C (e.g., approximately 5μΑ) is provided from the first current limit stage 76 through N ₉ ; and (b) a current I _C ci (e.g., approximately 39uA) is provided from the voltage V _P via P _u . A first portion of the current I _C ci flows through P ₈ and N ₁₃ as a current I _C C ₂ (e.g., approximately 20μΑ) to the voltage V _N . A second portion of the current Icci, shown in FIG. 2 as a current I _LK (e.g., approximately 19μΑ), combines with the current IS _R C to flow through P ₇ as the current IS _NK (e.g., approximately 24μΑ) to the second current limit stage 78. Also, based on the current mirror configuration of P ₁₂ relative to Pu, and based on the current mirror configuration of N ₁₄ relative to N ₁₃ : (a) the current I _CC1 causes a current I _GS1 (e.g., approximately 78μΑ) to flow through P ₁₂ ; and (b) the current Icc ₂ causes a current IGS ₂ (e.g., approximately 40uA) to flow through N14. The current IGS ₂ can be a first portion of the current IGS _I , and a second portion of the current IGS _I can flow through N ₁₅ , which is shown in FIG. 2 as a first output current Ιοτι (e.g., approximately 38μΑ), based on the respective activation of P ₁₂ and N ₁₄ .

[0029] Also, because N ₁₆ is arranged as a current mirror with respect to N ₁₅ , and because N ₁₇ is arranged as a current mirror with respect to N ₁₃ , a second output current Ι ₀ τ ₂ flows through N ₁₆ , and a third output current Ιοτ ₃ flows through N ₁₇ . Further, a respective portion of the output currents Ιοτ ₂ and Ιοτ ₃ is provided as an output node current Ι ₀ υτ, which is shown in FIG. 2 as flowing from the output node 90, such as to external circuit components (e.g., a capacitor). The third output current Ιοτ ₃ and the output node current Ιουτ can be equal to a sum of the second output current Ιοτ ₂ and the first output current Ιοτι. In the example of the input voltages VIN P and VIN N being approximately equal in a negative feedback condition (e.g., the output voltage VOUT can be coupled as the input voltage VIN _N in a voltage-follower configuration), the amplifier circuit 50 can provide the output voltage VOUT without sourcing any current from or sinking any current into the output node 90 from external circuit components. Therefore, in the example of the input voltages VIN P and VIN N being approximately equal, the output node current Ιουτ can be approximately equal to zero, such that the third output current Ιοτ ₃ (e.g., approximately 1mA) can be equal to a sum of the second output current Ιοτ ₂ (e.g., approximately 962 μΑ) and the first output current Icm.

[0030] In another example, the output node 90 can be short-circuited to ground or a reference voltage, and the input voltages VIN p and VIN N can have amplitudes that are not equal. For example, the input voltage VIN P can be greater than the input voltage VIN N ( ^e -g-, by approximately 700mV). Based on the difference between the input voltages VIN P and VIN _N, the voltage Vswi can be greater than the voltage Vsw ₂ , which can thus result in the voltages V _B1 and V _B2 having a relatively low amplitude. As the voltages V _B1 and V _B2 decrease in amplitude: (a) P ₇ of the cross-coupled pair of N ₁₀ and P ₇ has a stronger activation (e.g., P ₇ operates in the linear region, and the current ISNK achieves a maximum (i.e., limit) amplitude, resulting in a lower activation resistance RDS ON) than in the normal operating condition (e.g., described previously); and (b) Nio of the cross-coupled pair of Nio and P ₇ operates as a cascode stage to conduct the ISNK as a current I _L K, because the difference between the voltages VREFI and VB2 increases, while the voltage V _RE F _! remains at the same amplitude, and while the voltage VCOM decreases, resulting in the gate-source voltages of both Nio and P ₇ increasing. Also, a lower amplitude of the voltages V _B1 and VB ₂ results in deactivation of N9 and Pg, because the difference between the voltages VBI and VREF ₂ decreases, which results in the gate-source voltages of both N9 and Pg decreasing.

[0031] Based on the cross-coupling of Nio and P ₇ with respect to N9 and Pg, the voltage VCOM decreases in response to the low amplitudes of the voltages V _B1 and V _B2 , thus likewise activating Nio and P ₇ and deactivating N9 and Pg. Therefore, the current ISRC is deactivated, and the entirety of the gain current I _CC1 is sunk to ground as the currents I _L K and ¾NK (e.g., the currents Icci, ILK and ISNK can be equal with an amplitude of approximately 1mA). For example, the amplitude of the currents Icci, ILK and ISNK can have an amplitude that is a maximum amplitude defined by the current IL ₂ that flows through Nn in the second current limit stage 78, and based on the respective gate widths of the transistors through which the respective currents Icci, ILK and ISNK flow.

[0032] Based on the current mirror configuration of P ₁₂ relative to Pn, the current Icci causes a current IGSI (e.g., approximately 2mA) to flow through P ₁₂ . Based on the deactivation of Pg, the N-FETs Ni3, Ni4 and N ₁₇ can also be likewise deactivated. Therefore, the currents Icc2, IGS2 and IOT3 can be zero. The current IGSI can therefore flow in its entirety through N ₁₅ as the first output current Ιοτι to be combined with the second output current I0 _T2 (e.g., approximately 50mA based on a relative gate width of Ni ₆ ). Also, therefore, the output node current Ιουτ can flow from the output node 90 at an amplitude that is limited to a maximum amplitude (e.g., approximately 52mA) based on the limit amplitude of the gain current ISNK (e.g., 1mA), as defined by the second current limit stage 78. Accordingly, the amplitude limit of the output node current Ιουτ defined by the second current limit stage 78 can substantially mitigate damage to the amplifier circuit 50 and/or to circuit components coupled to the output node 90.

[0033] As yet another example, the output node 90 can be short-circuited to ground or a reference voltage, and the input voltage VJN_N can be greater than the input voltage Vi _N p (e.g., by approximately 700mV). Based on the difference between the input voltages VIN P and VIN _N, the voltage Vsw ₂ can be greater than the voltage Vswi, which can thus result in the voltages VBI and VB ₂ having a relatively high amplitude. As the voltages VBI and VB ₂ increase in amplitude, N9 of the cross-coupled pair of N9 and Pg has a stronger activation (e.g., N9 operates in the linear region, and the current ¾RC achieves a maximum (i.e., limit) amplitude, resulting in a lower activation resistance RDS_ON) than in the normal operating condition (e.g., described previously), and Pg of the cross-coupled pair of N9 and Pg operates as a cascode stage to conduct the ISRC as the current ILK (negative with respect to the example of FIG. 2), because the difference between the voltages VREF2 and VBI increases, while the voltage VREF2 remains at the same amplitude, and while the voltage VCOM increases, resulting in the gate-source voltages of both N9 and Pg increasing. Additionally, a higher amplitude of the voltages V _B i and V _B2 results in deactivation of Nio and P ₇ , because the difference between the voltages V _B2 and V _REFI decreases, which results in the gate-source voltages of both N ₁₀ and P ₇ decreasing,

[0034] Based on the cross-coupling of N ₁₀ and P ₇ with respect to N ₉ and P ₈ , the voltage VCO _M increases in response to the high amplitudes of the voltages V _BI and V _B2 , thus likewise activating Pg and N9 and deactivating N ₁₀ and P ₇ . Therefore, the current ¾ _NK is deactivated, and the gain current IS _R C is provided through the first gain stage 66 as the currents I _LK (i.e., negative with respect to the example of FIG. 2) and Icc2 (e.g., the currents IS _R C, I _LK and Icc2 can be equal with an amplitude of approximately 1mA). For example, the amplitude of the currents 1<χ ₂ , I _LK and IS _R C can have an amplitude that is a maximum amplitude defined by the current In that flows through P9 in the first current limit stage 76, and based on the respective gate widths of the transistors through which the respective currents lea, I _LK and IS _R C flow.

[0035] Based on the current mirror configuration of N ₁₄ relative to N ₁₃ , the current Icc ₂ causes a current IGS ₂ (e.g., approximately 2mA) to flow through N ₁₄ . Based on the deactivation of N ₁₀ , the P-FETs Pn and P ₁₂ can also be likewise deactivated. Accordingly, N ₁₅ and N ₁₆ can also be deactivated. Therefore, the currents Icci, IGS _I and I0T2 can be zero. The current IGS2 can therefore flow as a portion of the output node current Ιουτ (i.e., negative with respect to the example of FIG. 2) from the output node 90 as the first output current Ιοτι (i.e., negative with respect to the example of FIG. 2) through the diode Di. The remainder of the output node current Ι ₀ υτ can be provided as the third output current Ι ₀ τ ₃ (e.g., approximately 50mA based on a relative gate width of N ₁₇ ). Therefore, the output node current Ι ₀ υτ can flow into the output node 90 at an amplitude that is limited to a maximum amplitude (e.g., approximately 52mA), based on the limit amplitude of the gain current IS _R C (e.g., 1mA), as defined by the first current limit stage 76. Accordingly, the amplitude limit of the output node current Ιουτ defined by the first current limit stage 76 can substantially mitigate damage to the amplifier circuit 50 and/or to circuit components coupled to the output node 90.

[0036] FIG. 3 illustrates an example of an HDD system 150. The HDD system 150 can be implemented in a variety of computer applications for writing data to and reading data from a hard-disk drive. The HDD system 150 includes a magnetic disk 152 that acts as a spinning magnetic storage medium to which data can be written and from which data can be read. The HDD system 150 also includes a spindle motor (SPM) 154 that is configured to spin the magnetic disk during disk write/read operations. A head 156 is configured to perform the read/write operations with respect to the magnetic disk 152 based on positioning over the magnetic disk 152. The positioning of the head 156 can be provided in a precise manner by a voice coil motor (VCM) 158 and a dual-stage actuator (DSA) 160. The DSA 160 can receive actuator signals from a servo controller 162, such as can be implemented as at least a portion of an integrated circuit (IC) as part of control electronics 164 that are configured to control the HDD system 150. The servo controller 162 includes a VCM driver 166 configured to control the VCM 158, an SPM driver 168 configured to control the SPM 154, and a DSA driver 170 configured to control the DSA 160. In the example of FIG. 3, the DSA driver 170 includes a voltage amplifier 172. For example, the voltage amplifier 172 can be configured substantially similar to the amplifier system 10 in the example of FIG. 1 or the amplifier circuit 50 in the example of FIG. 2.

[0037] For example, the DSA driver 170 can be configured to provide the actuator signals that can be amplified by a voltage amplifier 172 to the DSA 160 to provide precise positioning of the head 156 over the magnetic disk 152. Therefore, the voltage amplifier 172 can provide an amplified output voltage that corresponds to an input voltage, such as a differential input voltage. Furthermore, the voltage amplifier 172 can be configured to exhibit current limiting with respect to an output current, such as by including at least one current limit stage. Therefore, damage to the voltage amplifier 172 and/or the DSA 160 from excessive current, such as based on an associated output of the voltage amplifier 172 being short-circuited, can be substantially mitigated.

[0038] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.