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Title:
DATA PROCESSING APPARATUS
Document Type and Number:
WIPO Patent Application WO/2020/027785
Kind Code:
A1
Abstract:
A data processing apparatus is configured to solve a specific problem using a simple hardware. The data processing apparatus comprises a state data processing unit configured to iterate update of state data by a predetermined time evolutional process, a cost evaluation, unit configured to evaluate a cost function for current state data, and an error calculation unit configured to calculate error values relating to amplitude homogeneity of the current state data, wherein the state data processing unit performs the time evolutional process on the state data to update the current state data based on the cost function and the error values which are calculated by the error calculation unit.

Inventors:
LELEU TIMOTHEE GUILAUME (JP)
AIHARA KAZUYUKI (JP)
MCMAHON PETER (US)
YAMAMOTO YOSHIHISA (JP)
Application Number:
PCT/US2018/044469
Publication Date:
February 06, 2020
Filing Date:
July 31, 2018
Export Citation:
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Assignee:
UNIV TOKYO (JP)
JAPAN SCIENCE & TECH AGENCY (JP)
UNIV LELAND STANFORD JUNIOR (US)
International Classes:
G05B13/00
Foreign References:
US20090210081A12009-08-20
US20170024658A12017-01-26
US20080065573A12008-03-13
US20150032994A12015-01-29
Attorney, Agent or Firm:
IMAIZUMI, Toshikatsu (US)
Download PDF:
Claims:
WHAT IS CLAIMED IS

1. A data processing apparatus which is configured to solve a given problem comprising:

a state data processing unit configured to iterate update of state data by a predetermined time evolutional process ;

a cost evaluation unit configured to evaluate a cost function for current state data; and

an error calculation unit configured to calculate error values relating to amplitude homogeneity of the current state data;

wherein the state data processing unit performs the time evolutional process on the state data to update the current state data based on the cost function and the error values which are calculated by the error calculation unit.

2. The data processing apparatus according to claim 1,

wherein the state data processing unit performs the time evolutional process on the state data to update current state data based on a gradient of the cost function and the error values,

and wherein the time evolutional process on the state data also updates the current state data based on the archetype potential that is changed from monostable to bistable according to the gain value.

3. The data processor apparatus according to claim 1,

wherein the error calculation unit is also configured to calculate at least one error value relating to

constraints of a problem to be solved.

4. The data processing apparatus according to claim 1, wherein the state data processing unit also performs projection of the state data onto a predetermined subspace.

5. The data processing apparatus according to claim 1,

a1so comprising :

a modulation unit configured to perform calculation of a target amplitude based on the current state data,

and wherein

the error calculation unit calculates, taking

advantage of the target amplitude, error values which is related to amplitude homogeneity of the current state data.

6. The data processing apparatus according to claim 5,

wherein the state data processing unit also performs projection of the state data onto a predetermined subspace defined by the target amplitude.

7. The data processing apparatus according to claim 1,

also comprising:

a modulation unit configured to perform calculation of a gain value based on the current state data,

and wherein,

the state data processing unit is also configured to update archetype monostable/bistable potential with the gain value calculated based on the current state data.

8. The data processing apparatus according to claim 1,

also comprising:

a modulation unit configured to dynamically determine a change rate of the error values, and wherein the error calculation unit performs the time evolutional process on the error values to update the current error values based on the change rate of the error values, the error values, the state data, and the cost functio

9. The data processing apparatus according to claim 7,

wherein the gain value also depends on constant values that are calculated using the parameters of the cost

function prior to the start of the time evolutional process.

10. The data processing apparatus according to claim 1,

wherein the state data processing unit performs the time evolutional process on the state data to update the current state data based on the cost function by using an Ising model quantum computation device, the Ising model quantum computation device comprising:

a parametric oscillator that parametrically

oscillates a plurality of pseudo spin pulses, the plurality of pseudo spin pulses being in correspondence wit a

plurality of Ising model spins in a pseudo manner and having mutually an identical oscillation frequency;

a ring resonator in 'which the plurality of pseudo spin pulses circularly propagate;

a tentative spin measuring unit that tentatively measures phases and amplitudes of the plurality of pseudo spin pulses every time the plurality of pseudo spin pulses circularly propagate in the ring resonator to tentatively measure pseudo spins of the plurality of pseudo spin pulses ;

a FPGA device configured as calculate, according to the output of the cost evaluation unit and the error values, the data which is to be synthesized to the measured pseudo spin pulses to obtain the time evolution of the state data, and output the result of the time evolution of the state

Ό-c ta .

Description:
DATA PROCESSING APPARATUS

Background

Technical Field

The present invention relates to a data processing unit that solves combinatorial optimization problems .

Related Arts

In order to solve combinatorial optimization problems, classical digital computers employ algorithms that are compiled to run on general-purpose central processing units (CPU) . For many years, it has been possible to miniaturize the digital hardware (e.g., the number of transistors in a CPU) at a rapid pace. However, the limits of the minimization of digital components are nearly reached, as the very tightly packed transistors cannot be made to get enough energy efficiency while functioning robustly. From a theoretical viewpoint, the computational process employed by these classical computers can generally be described in the framework of the von Neumann architecture .

Given that computation by these classical computers can be formalized using the Turing machine, these have "universal" computing capabilities as proven by the Church- Turing thesis, only when resource limitations are ignored . In addition to the limit of the number of logical operations performed by the CPU described here-above, the finite bandwidth between CPU-uni t and memory is another well-known bottleneck limiting information flow in these computers .

In order to circumvent the limitations of classical computers, it has been proposed to consider "nonconventional" data processors. These novel computers do not necessarily have universal computing capabilities, but are optimized for specific computational tasks . Gain in performance can be achieved by implementing the processing of information directly using lower-levels of abstraction that are close to the physical layer, rather than relying on the higher levels. Computation at the lowest levels cam now be achieved using "soft" data processors whose internal structure is dynamically reorganized in order to fit a specific purpose. This allows notably to perform massive parallel computation, in which memory and processing are collocated.

Moreover, it has been proposed to utilize the analog signals of the data processors directly, rather than the binary states used in classical computers. The analog state can be implemented physically in the electronic domain by, for example, electronic components operating in the subthreshold regime, or using non-linear optics. Although such analog computers can be simulated by digital ones in theory, they allow much faster processing for certain type of dedicated problems, notably the ones that involve simulating differential equations. The underlying motivation for developing such device is that the physical units of the hardware that are used for computation can encode much more information than just Os and Is. Thus, gain in resources can be obtained by computing directly at the lower physical level, rather than only at the higher logical one.

In particular, recently proposed analog computers such as the analog Hopfield neural networks (US patent US 4660166) or optical analog computers such as the Coherent Ising Machine (such as US Patent US 9411026) can solve combinatorial optimization problems approximately.

Currently, these machines allow taking advantage of the parallel calculation achieved by the analog hardware in order to do fast computation (US patent US 4660166) . It is also interesting to underline the conceptual proximity of these devices with neural networks. Recent advances in the field of computational neuroscience can be applied for developing novel analog computing schemes that are inspired by analog processing occurring in the brain.

Unconventional neuro-inspired data processors such as GPUs (Graphics Processing Units), Tensor Processing Units (TPUs), FPGAs, etc., have been applied successfully to the field of classification and outperforms state-of-the art methods that employ classical hardware, as exemplified by the recent trend in deep learning networks.

However, analog neural networks, descried above, have two limitations. First, although they can find good approximate solutions to combinatorial optimization problems by mapping the cost function (or objective function) to the system's energy function (or Lyapunov function, which is defined usually when connections are symmetric) , they do not guarantee in general finding the optimal solution to combinatorial optimization problems. Indeed, these systems can get caught in local minima of the energy function in the case of non-convex problems. Analog neural networks are usually dissipative systems, and it has been proposed in the framework of the Coherent Ising machine to improve the solution quality by setting the gain of the system to its minimal value, at which only the solution with minimal loss is stable, and other configurations are unstable. But, the fact that the amplitudes of analog variables are in general heterogeneous ( i . e . , not all equal ) result in the wrong mapping of the obj ective function by the energy function, and operation at the minimal loss regime is not guaranteed to converge to the optimal solution of a given combinatorial optimization proble .

For the second limitation; the constraints imposed in constrained optimization problems, which are usually converted into soft constraints by adding penalty terms in the cost function, cannot be properly taken into account . Indeed, using soft constraints (i.e., penalty terms) is known to result in convergence problems, notably because the penalty terms tend to interfere with one another in the summation of the global cost function . Moreover, the penalty terms usually have very different scales that must be corrected using carefully chosen constant coefficients.

Various schemes have been proposed in order to resolve these issues. In the case of the popular simulated annealing scheme, which is a stochastic search over the digital states, the convergence to the optimal solution is assured when the "temperature" of the system is gradually decreased at the proper rate. Although the convergence can be proven analytically, it is in practice difficult to find the optimal scheduling that allows solving efficiently a given combinatorial optimization problem (L. Ingber, Mathematical and computer modelling, 18, (29) , 1993) .

There is also the concept of computation close to the physical layer which also extends to (quantum and) quantum analog devices, which aim at taking advantage of quantum dynamical properties of the hardware . There have been recent attempts at building quantum annealing devices, in which the strength of an initially strong transverse field is gradually decreased. In the limit of the adiabatic regime, such system remains in the ground-state and reaches the state encoding for the optimal solution of the combinatorial optimization problem once the transverse field vanishes. Real physical implementation of such machine, such as proposed by D-wave (for example, US patent US 6803599) , suffers from interactions with the environment that destroys quantum effects in these devices, and is limited to special topology of connections (chimera graph) between its components that requires an embedding of the combinatorial optimization problem into this topology that is costly in resources. Because of these limitations, it has not been widely recognized that such quantum devices offer an important computational advantage compared to analogous classical methods such as simulated annealing for solving general types of problems.

As discussed above, in the related arts, it is becoming hard to improve the speed for solving a specific problem with a simple hardware in both digital and analog computing devices. Thus, there is a need for a computing device that can solve a specific problem fast with a simple hardware ,

Summary

The present invention provides, a data processing apparatus which is configured to solve a given problem, comprising :

a state data processing unit configured to iterate update of state data by a predetermined time evolutional process;

a cost evaluation unit configured to evaluate a cost function for current state data; and

an error calculation unit configured to calculate error values relating to amplitude homogeneity of the current state data;

wherein the state data processing unit performs the time evolutional process on the state data to update the current state data based on the cost function and the error values which are calculated by the error calculation unit. According to the present invention, a computing device that can solve a specific problem fast with a simple hardware can be provided.

Thus, there are a number of advantages and there is no requirement that a claim be limited to encompass all of the advantages ,

In addition, the foregoing has outlined rather broadly the features and technical advantages in order that the detailed description of the invention that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims ,

Brief Description of the Drawings

For a more complete understanding, and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings.

Fig. 1 illustrates the schematic structure of the data processing apparatus of an embodiment of the present invention .

Fig. 2 illustrates the example of functional structure of the data processing apparatus of an embodiment of the present invention .

Fig, 3 illustrates the schematic structure of the error calculation unit of an embodiment of the present invention .

Fig. 4 illustrates an example of the state data processor of an embodiment of the present invention.

Fig. 5 illustrates a schematic functional structure of an embodiment of the present invention.

Description of Embodiments

A description will now be given, referring to embodiments thereof. While the claims are not limited to such embodiments, an appreciation of various aspects of the invention is best gained through a discussion of various examp1es thereof .

One of the preferred embodiments of this invention is, as shown in FIG. 1, a data processing apparatus 1 which comprises a processor 11, and an input-output device 13. In this embodiment, similar to Ising machines and Hopfield neural networks, the data processing apparatus 1 includes state-encoding units, in which the binary variables of a combinatorial optimization problem are mapped to analog variables, as described later. In addition to this, the data processing apparatus 1 also includes another subsystem, called error-encoding units, that corrects the mapping between the steady-stat.es of the data processing apparatus 1 and the configurations of lower cost values of the combinatorial optimization problem, and the state-encoding units are connected asymmetrically to the error-encoding units.

The processor 11 may be a FPGA which includes logic gates and memory blocks. In this embodiment, the processor 11 is configured to iterate update of the state data by a predetermined time evolutional process, to evaluate a cost function for the state data, and to calculate an error value relating to amplitude homogeneity of the state data. When updating the state data, the processor 11 also take advantage of the error value and the cost function. The detail process in the processor 11 will be described later.

The memory block in the processor 11 may store the data used in the process in the logic gates of the processor 11, such as the state data.

The input-output (I/O) device 13 may include an input device such as a keyboard, a mouse, and the like. The I/O device 13 may also include a display to output information such as the state data, the value of the cost function, or the like according to instructions from the processor 11.

The processes in the processor 11 are described hereinafter. In the following example, the problem to be solved by the data processing apparatus 1 according to an embodiment of present invention is a combinational optimization problem. In the combinational optimization problem, a cost function is defined, and as the cost function of the combinatorial optimization problem is minimized, the combinatorial optimization problem is solved

Here, the cost function is denoted by V' IJ) (s) , where a real number for any vector s, and the vector s (i = 1, 2, N) , with s ± =±1. The cost function defined by the set of parameters {Mnih (i :=: 1, 2, M 0 r is a vector, a matrix, or, more generally, cL tensor. The number of Boolean variables (or size of the problem) is denoted by N.

In the case of constrained optimization problems, acceptable solutions constitute a subset, denoted by S, of the whole space of configurations. Depending on the constraints of a given combinatorial optimization problem, the subset S can be defined using equality and/or inequality constraints given as follows :

(equality constraints)

, (inequality constraints) (1) here, k, k' = :: 1, 2, ..., K.

The matrices and vectors A k , C k , b k , and d k are defined by another set of parameters denoted by {N ki h or {M ki h where k is the index of the constraint with k =1, 2, ..., K, i==l,

The constraints are classified into two categories .

The first set of constraints, called soft constraints of type I, are realized by adding penalty terras to the cost function and proj ecting the system in a valid subspace defined by these constraints. The total cost function v that takes into account these constraints is given as follows :

where U !K) is the penalty term that is imposed by the constraint k. Here, q k is a constant positive parameter for k =1 , 2 , Ki, and K ]; is the total number of constraints in this subset . The value of the penalty term (o) is minimal when the vector s satisfies the constraint k. The penalty terms U (k ' (a) are functions which depend on the parameters {M ki}i , and the proj ection P to the valid subspace, and must be given as an input to the proposed system.

The second set of constraints, called soft constraints of type II, are realized using an error-detection/error- correction feedback loop . Penalty terms V tK) , which depend on parameters {N ki}i , with k=l, 2, ..., K n , (and let K t + K n = K) , must also be defined, and are used for error correction Moreover, functions g k , which are positive when the constraints are not realized, are used for error detection.

1 The functions g b are negative, when the constraints are realized.

The choice of U' K) , V' K) , P, and gy depends on the combinatorial problems to be solved and their constraints. In other words, the U ) , V (k ' , P, and g k are set by the user of the data processing apparatus 1.

An exemplary functional construction of the processor 11 is shown in FIG. 2. As shown in FIG. 2, one of the examples of the processor 11 is configured to be functionally include a state data processor 21, a cost evaluation unit 22, an error calculation unit 23, a modulation unit 24, and an output unit 25.

The state data processor 21 is configured to iterate update of state data by a predetermined time evolutional process . The state data is a set of fixed point variables Xi ( i=l , 2, ...N) , which is obtained by, for example, encoding the analog state.

The state data processor 21, in this embodiment, iterates update of state data by a predetermined time evolutional process, projects the updated state data onto the valid subspace, and stores the projected updated state data, as new state data, in the memory block.

Specifically, the state data processor 21 has processing units 210, a gain-dissipative simulator 211, and a projection unit 212. Each processing unit 210 is provided for processing state data x, (i=l, 2, ...N) , respectively. The gain-dissipative simulator 211 is an isolated (non-coupled) unit . The gain-dissipative simulator 211 gets state data x, and a linear gain p, and calculates a gradient descent of the potential V b . The calculation can be simplified to the following ordinary differential equation system that describe a gradient descent when b = 0:

3 tXi = f(xi) + b. (3)

where f (xi) = - 5V b /3xi and V b is the energy function or

Lyapunov function of the isolated (non-coupled) units, such as a potential function :

The energy function V b represents the paradigmatic bistable potential (archetype monostable/bistable potential) which can be monostable (when pel) or bistable (when p>l ) according to the value of the linear gain p . When V b is bistable, the state data xi converge to binary states at the lowest points of the potential V b when v ~ 0 Moreover, V represents an external analog injection signal to the i-th processing unit 210. The external analog injection signal will be described later.

The formula (3) can be rewritten as follows:

3 t i = (-1 + p)x± - x J i + I±, (4)

in which -xi, pxi, and -xh represents the terms related to the loss, the linear gain, and saturation of the state x, respect ive1y ,

Note that the dynamics are described herein in the continuous···time domain using ordinary differential equations (ODEs) , but that the system can also be operated in the discrete-time domain. The conversion from continuous to discrete time can be obtained by a simple Euler approximation, or the like, of the ODEs describing the system.

The coupling between the processing units 210 of the state data processor 21 is implemented using the injection term L· given as follows:

In the formulae (4) and (5), vector e ' " 0 (whose elements are eh^, i=l, 2, ...) are the error signals; V * is the cost function with penalty terms that take into account soft constraints of type I; and V' * ’ are the penalty terms related to the kth soft constraint of type II. Lastly, are positive real parameter values. The types of constraints are described later.

The effect of the input Ii is to impose a gradient descent of the potentials V (ki (x) . Note, however, that the gradient 3V i ! (x) /dx is modulated by ei <J , i . e . , the gradient vector is defined using the state-space, and is rescaled by the error signals. Each error signal eh' x! rescales the space vector x differently according to the constraint being imposed.

Lastly, the gradients are summed over the indices k, taking into account the soft constraints of type II . Therefore, multiple constraints are in competition in the sum. A given constraint eventually wins when the amplitude of its rescaled gradient vector becomes much larger than the other ones.

The Projection unit 212 performs projection of the state data onto a predetermined subspace. Specifically, in this embodiment, the state data vector x is projected onto the valid subspace at each iteration of updating the state data vector x using a projection operator P which is predetermined according to the constraints of type I.

The projection is similar to Aiyer' s method for the Hopfie1d Net ork .

The effect of the projection operator can be described by considering the Euler steps of the time-evolution of vector x given as follows:

If there are no soft constraints of type I, the projection P is the identity operator, and the vector x’ is equal to the vector x.

Note that the time-evolution of the system can also be described in the continuous time domain using algebraic differential equations in order to take into account the projection P,

The cost evaluation unit 22 calculates the cost function of current state data. The error calculation unit 23 calculates at least an error value relating to amplitude homogeneity of the current state data. In this embodiment, the role of these error signals is to: (1) correct the heterogeneity in amplitudes of the state encoding units, and (2) allow an appropriate mapping of the constraints. Each error encoding unit is usually connected to only a subset of state-encoding units. Note that the correction of amplitude heterogeneity can be interpreted as an equality constraint of an optimization problem on the analog space.

In other words, combinatorial optimization on binary variables is an optimization problem on analog variables with the constraint that all amplitudes of the analog states are equal.

As shown in FIG. 3, the error calculation unit 23 includes an error calculation subunit 231 and a plurality of subunits 232.

The error calculation subunit 231 which calculates the error for amplitude heterogeneity, e i!J! , includes a time- evolution processor 2311 and an updater 2312. The time- evolution processor 2311 takes a target amplitude a with a > 0 and a rate of change of this error signal b 0 , which are specified by the user at least at the time of initialization, and gives the error signals e |0) , which is one of e lki of index k = 0 and that is related to the minimization of the cost function V * . These error signals correct the heterogeneity in amplitudes of the state data vector X.

Specifically, the time-evolution processor 2311 calculates the error signals e i0; as:

The updater 2312 updates the current ei i0i by adding 3 t ei <u! dt to get updated e ± { ! and stores eh' 0i in the memory block as the error signal for the next iteration.

Each one of the subunits 232 which calculates the error for constraints also includes a time-evolution processor 2321 and an updater 2322. The time-evolution processor 2321 takes a target function gi and a rate of change of this error signal bi, which are specified by the user at least at the time of initialization, and gives the error signals e which is one of e ; of index k = i and that is related to the minimization of the cost function V * These error signals enforce the constraints of the problem upon the state data vector x.

Specifically, the time-evolution processor 2311 calculates the error signals e ! as :

d t

where the x is the vector of the state data, and g ix) ( ei 1 " ! , x) is related to a constraint of the problem to be solved.

Note that if there are no constraints according to the problem to be solved, any subunits 232 are not always required .

The updater 2322 updates the current ei (k! by adding d t ei'^’dt to get updated ei (k! and stores eh^ in the memory block as the error signal for the next iteration .

The error calculation unit 23 outputs current error values ei (k ' (i=0, 1,2...) to the state data processor 21.

The modulation unit 24 performs calculation of parameter values such as a linear gain p, a target amplitude a, and a rate of change of error values b> ; based on the current state data . If the modulation unit 24 gives the parameters such as a target amplitude to the error calculation unit 23, the error calculation unit 23 may take advantage of the parameters given from the modulation unit 24 , instead of values which are designated by a user .

In this embodiment, the modulation unit 24 converts the analog state x into an acceptable Boolean configuration s, with s = C [x] , at each step of the computation. Next, the modulation unit 24 takes advantage of this configuration in order to calculate the current value of the cost function \d C) Lastly, the modulation unit 24 modulates the linear gain p and the target amplitude a as fol lows

Here, V l ° ! (t) is the value of the cost function associated with the state x ( t ) , and V op ! is the target energy. In an example, can be set to the lowest energy found during iterative computation, i.e.

or can be set to the minimum value of the cost function V' 0> if it is known. The function is a sigmoidal function, and

are constant predetermined parameters . Note that other- parameters, such as the rates

can also be modulated.

The efficiency of the proposed scheme depends on the choice of parameter values for

and others .

It will be shown that the parameters can be chosen without prior tuning by using the spectral decomposition (the maximum eigenvalues) of the coupling matrix.

The output unit 25 outputs current state data x. The output unit 25 can be configured to output a cost function for the current state data in addition to the state data.

In an embodiment of the present invention, a data processor includes the error correction scheme described above. Error detection is achieved by, for example, considering auxiliary analog dynamical variables called error signals . A set of error correcting variables is used for correcting the amplitude heterogeneity that results in the wrong mapping of the objective function by the system.

Moreover, another set of variables and the projection on a valid subspace is considered for imposing constraints of the optimization problems. The error control utilizes asymmetrical error-correction, and error detection feedback loop .

Lastly, the dynamics of the error signals generally depends on the current Boolean configuration, which is in turn encoded by the analog state, in order to detect errors at the logical level. However, the error signals themselves are analog and modify the current state-encoding variables in an analog way.

For showing an operation of the data processor of the embodiment, some specific examples for solving problems will be described below.

(1) Example of the maximum cut problem

The proposed architecture used in the max-cut problem will be illustrated. The data processing apparatus 1 for the max-cut problem is configured to find the cut of the graph defined by the weights

for which the sum over the weights is maximal. Here i and j are one of the natural numbers below N: 1, 2 , ..., N.

A given solution for the max··· cut problem can be represented by a partition of the vertices i, into two sets obtained after the cut. The belonging of the vertex i to one or the other set is encoded by a Boolean variable l solution of the problem, or max-cut, nimizes the cost function

The max-cut problem is a quadratic unconstr?.lined binary combinatorial optimization problem, or Ising prc>b1em Note that the parameters of the cost function consis t of the matrix, and the total cost function V * consists of only one matrix:

In the case of the max-cut problem, there are no constraints. Thus, the data processor for this example has only N state data processors 21 which correspond to state data xi (1=1, 2, N) . The data processor for this example also requires only N error calculation units 23 which correspond to the error data ei (0; for correcting the amplitude heterogeneity when solving the problem of size N.

In this example, the projection operator P is identity:

In addition to that, the conversion to acceptable solution is achieved by defining: In this example, in the processor 11 of this embodiment, the state data processor 21 initializes the state data xi (1=1, 2, ...N) by a predetermined method, for example, by generating a random Boolean value for xi .

Once the state data is set, the cost evaluation unit 22 evaluates a cost function for current state data. In this example, the cost function is set to

where the Hamiltonian is the ising Hamiltonian:

is the weight which is initialized randomly at the first time of iteration.

Meanwhile, the error calculation unit 23 calculates error values relating to amplitude homogeneity of the current state data.

The time-evolution processor 2311 of the error calculation unit 23 takes a target amplitude a (a>0) and a rate of change of error values b , which are initially (at t=0} set to predetermined values, such as a=1.0 and b (t=0 ) = 0.0.

Taking advantage of these values , the time-evolution processor 2311 calculates the time-evolution of the error

wherein the erro values ί 0 )

Oi for the first. time of iteration are set to random numbers.

The updater 2312 updates the current error values ei l0) by adding 3 t ei l dt to get updated error values ei l , and outputs the updated error values ei (0i to the state data processor 21.

Then, the gain-dissipative simulator 211 of the state data processor 21 gets the state data x i a linear gain p, and the error values ei (0! to calculate the time-evolution of the state as:

In this formulae, the time dependency is not explicitly shown, but the values such as the state data Xi and the error values b ± ίύ> change depending on time t.

The state data processor 21 updates the state data by adding corresponding state data x ± and the time-evolution of the state data:

The state data processor 21 stores the updated state data Xi (t+dt) as the current state data . It must be noted that in this problem, there are no soft constraints of type I, the proj ection P is the identity operator, and the vector x’ is equal to the vector x:

x' = x

and the updated state data is stored as the current state data in the next iteration as they are .

Before the next iteration of updating state data, the modulation unit 24 performs calculation of parameter values such as a linear gain p, a target amplitude a, and a rate of change of error values b based on the current state data The modulation unit 24 converts the state data x into an acceptable Boolean configuration s. In this example, since the state data x is already Boolean values, the modulation unit 24 calculates the current value of the cost function V (0; , and the modulation unit 24 modulates the linear gain p and the target amplitude a as represented by

and the rate

is also modulated in the same manner.

is a sigmoidal function, and

are constant predetermined parameters.

The Parameter values

are predetermined by the user.

Here, V i ) (t) is the value of the cost function associated with the state data x(t) which is evaluated by the cost evaluation unit 22, and V opt (0 ' is the target energy In this example, V opt ' 0 ' is set to the lowest energy found during the iterative computation:

p the modulation unit 24 memorizes the current V opt ' 0 ' and updates the V opt (&! when the current V i0 ’ (t) is lower than the memorized V opt (0 ' . At the initial state, since the modulation unit 24 does not memori ze any V opt l °' , the modulation unit 24 simply memorizes a calculated V ' ; (t=0) .

The modulation unit 24 gets the updated linear gain p the target amplitude a, and the rate and outputs those.

The processor 11 outputs the current updated state data x and the cost function, and then proceeds to the next iteration step.

The cost evaluation unit 22 evaluates the cost function for current (updated) state data, and the error calculation unit 23 calculates the error values relating to amplitude homogeneity of the current state data.

The processor 11 iterates the process, that is, the processor 11 calculates the time-evolution of error values :

time-evolution of the state data :

and update the state data as:

The processor 11 stores the updated state data xi (t+dt) as the current state data.

And then, the processor 11 performs calculation of parameter values such as a linear gain p, a target amplitude a, and a rate of change of error values bk, based on the current state data.

The processor 11 outputs the current updated state data X and the cost function, and repeats the process until the cost function satisfies a predetermined condition, such that the cost function is lower than a predetermined threshold, or until the user stops the process.

In the case of the max-cut problem, the dynamics of the data processing apparatus 1 cam be summarized as follows:

These equations are obtained from calculating the gradient of

Moreover, the target amplitude a is chosen as follows in order to assure the convergence to the optimal solution: onfiguration ( current state anci

is the target energy. In practice the target r j ø j · :gy can be set to the lowest energy found:

or can be set to the ground state energy if it is known,

Moreover. the function f is a sigmoidal function and both constant parameters which are preset by the user.

For further shortening of the time-to-solution, it is considered that the parameter is time-dependent. It is linearly increased with a rate equal to during the simulation, and reset to zero if the energy does not decrease during a duration

where, t c represents the time when the best known energy r when

gn ent pro^ e ( QAP ) gnment

is s gning n tac

total ommoditi distances and times flows between factories, is minimized. In order to encode this problem in an objective function, Boolean variables si u will be defined such that s iU = 1 if the factory u is assigned to the site i; s iu = 0, otherwise Then, solving this problem consists in finding a configuration that minimizes the following cost function

represents flows between factories u and v, and the matrix { } i- j (whose (i,j)-th element is a ± ) represents distance bet een sites i and j .

Note that eling salesman problem is a special case of GAP .

By considering the change of variable -

0.5), this objective function can be mapped to the following cost function:

w ere s e cos unc on o e m n m ze , an U are soft constraints of type I related the first constraint (one factory per site) and second constraint (one site par factory) , respectively. Moreover, q is a positive parameter predetermined by the user. Each cost function can be expressed as:

22) ize

are all is the vector of size N whose components are all 1.

The A and B are matrices whose components are ai j and bi j respectively, and I is the identity matrix of size

Note that the Ising coupling is the cost function for this problem, and the parameters of the cost function depends on the tensor products of the matrices.

The parameters characterizing the cost functions

ameter characterizing ana

In the case of QAP, all constraints are considered as type I. Thus the processor 11 is configured to nave N state data processors 21 for state data x ir and to have N error calculation units 23 for e 1 for correcting the amplitude heterogeneity when a problem to be solved has the size N. Moreover, the cost function V is given as described as equation (21) , The valid subspace for this problem is defined as:

const defined

The valid subspace is thus the set of stochastic matrices { Xi U } i u ·

The projection operator P on the valid subspace can be determined by considering the eigendecomposition of the matrix

The conversion to acceptable solutions is achieved by associating a permutation matrix with each state data matrix {x iu }iu·

In this example, in the processor 11 of this embodiment, the state data processor 21 initializes the state data xi (1=1, 2, ...N) by a predetermined method, for example, by generating state data for one of allowed state (as a state data is in the valid subspace) .

Here, the state data xi represents Boolean variables S pq such that S pq = 1 if the factory q is assigned to the site p; s pq = 0, otherwise; where i = N site ( p-1 ) +q; N site is the number of sites.

The Projection unit 212 of the state data processor 21 performs projection of the current state data onto a predetermined valid subspace. Specifically, in this example, the state data vector x is projected onto the valid subspace using a projection operator P which is predetermined according to the constraints of type I to get x' . the proj ection operator P can be determined by considering the eigendecomposition of the matrix

are defined as equation (22) .

Once the state data is set, the cost evaluation unit 22 evaluates a cost function for current state data. In this example, the cost function V * is set to equation (21) .

Meanwhile, the error calculation unit 23 calculates error values relating to amplitude homogeneity of the current state data.

The time-evolution processor 2311 of the error calculation unit 23 takes a target amplitude a (a>0) and a rate of change of error values b, which are initially (at t=0) set to predetermined values, such as a=l .0 and b ( t=0 )

0.0. Taking advantage of chese values, the time-evolution processor 231: ca- ilates the gradient of the error values wherein the error ) for the first time of iteration are set etermined values .

The updater 2312 updates the current error values qi ίu! (t) by adding d t 101 (t) dt to get updated error values ei (t+dt) , the error values for next iteration, and outputs the updated error values ei (0! (t+dt) to the state lata processor 21.

Then, the gain-dissipative simulator 211 of the state data processor 21 gets the state data x’i (the state data pro ected onto the valid subspace), a linear gain p, and the error values 6i ί0; to calculate the time-evolution of the state as:

Here, hi 1 ) (t) is the i-th element of the vector h' b ' (t) which is defined as:

represents the average absolut itud of x The state data processor 21 updates the state data by adding corresponding state data xi and the gradient

The state data processor 21 stores the updated state data Xi (t+dt) as the current state data. It must be noted that in this problem, there are soft constraints of type I, and the Projection unit 212 of the state data processor 21 performs projection of the updated state data x using the projection operator P:

The projected state data x3 (t+dt) is stored as the current state data x(t) in the next iteration.

Before the next iteration of updating state data, the modulation unit 24 performs calculation of parameter values such as a linear gain p, a target amplitude a, and a rate of change of error values b 0 based on the current state da ta .

The modulation unit 24 converts the state data x into an acceptable Boolean configuration s by a formula such as O pq = 2 ( S pq -- 0.5), and the acceptable configuration respects the constraints of the quadratic assignment problem, i.e.,

The modulation unit 24 calculates the current value of one of the terms of the cost function V' IJ) , and the modulation unit 24 modulates the linear gain p and the target amplitude a as represented by formulae (12) and (13) :

is also modulated in the same manner. in the formulae,

is a sigmoidal function, and

are constant predetermined parameters.

The Parameter values

are predetermined by the user.

Here, V' 0) (t) is the value of one of the term of the cost function associated with the state data x (t) which is evaluated by the cost evaluation unit 22, and V pt iJ! is the target energy. In this example, V opt (0i is set to the lowest energy found during the iterative computation:

current V 10 ' (t) is lower than the memorized V opt ' IJ) · At the initial state, since the modulation unit 24 does not memorize any V opt (I i , the modulation unit 24 simply memorizes a calculated V

The modulation unit 24 gets the updated linear gain p, the target amplitude a, and the rate

and outputs those . The processor 11 outputs the current updated state data x and the cost function, and then proceeds to the next iteration step.

In the case of QAP, as shown above, the dynamics of the data processing apparatus 1 can be summarized as:

In the formulae, indices i, a represents i-th factory and a-th site, and here, the h <0 'i a is defined as formulae

(24) .

Although the calculation of h' 0 ' includes matrix vecto multiplications, such as

since the matrix size is N 2 by N , products of them are not computed directly in practice . Rather, the resul t of the products are computed by taking into account the fact that the matrices themselves are the results of tensor products.

wherein the [Q] represents a vector whose elements are those of Q,

(3) Architecture proposing using the lead optimization problem

The lead optimization problem is a problem to find a structure of compound candidate given that its geometry and constituting atomic species are known . That is, the objective of this combinatorial optimization problem is to assign atomic species to positions of the known geometry in order to minimize interaction energy with a given protein.

If the spatial structure has, for example, the form -X1-X2-X3-X4-X5-X6- can be chosen among =CH- , =CH2 ,

=0, =NH2 , ---OH, -CH3, (wherein each symbol "=" or represents chemical bond) then a possible solution is the chain -CH=CH-CH=CH-CH=CH- .

Structures candidate must satisfy two constraints: (1) the consistency between bonds of neighboring species must be satisfied, (2) only one atomic species can be assigned per position. In the following, the scope of this problem is restricted to finding candidate species that satisfy these two constraints, without taking into account interaction energies with the target protein, for the sake of simplicity .

The proposed architecture can be used to solve such constrained combinatorial optimization problem. First, state-encoding variables o r. = ±1 are considered which encode, when oi j T, = 1, for having the atomic species n active at the site i; otherwise n = -1. The two constraints described here-above can be converted into a Ising problem with cost function V given as follows:

(according to H. Sakaguchi, et, al . , "Boltzmann Sampling by Degenerate Optical Parametric Oscillator Network for Structure-Based Virtual Screening", Entropy, 18, 365(2016) ), where V (1 ' and V ) are cost functions of soft constraints related to the first constraint, which represents bond consistency, and the second constraint, which represents unicity, respectively.

In these formulae,

are the parameters defined user with considering the change of the variable or 1.

Finding a satisfiable structure is equivalent to minimizing the cost function V * .

In reality, the cost functions V (1! and V ) of soft constraints are also written as:

Here, if the sites i and j are adjacent, and the bonds of the atomic species n at position i are not compatible with the ones of atomic species m at position j, Ji n m. = 1.

On the other hand, if the sites i and j are not adjacent, or the bonds of the atomic species n at position i are compatible 'with the ones of atomic species m at position j , J injm = 0.

Ci and C? are constant values that are independent of si n and do not matter for the combinational optimization problem.

Since the operation of the data processing apparatus 1 will be in the same manner as described in the examples of max-cut and QAP, the redundant explanation will be omitted.

In this example, the data processing apparatus 1 may be configured to operate on the following dynamics:

The formulae (34) represents bond consistency, and the formulae (35) represents unicity.

Here,

and Ei„>0 when atom n at position i is inc c i Sortp(ri

are change rates of error values for ei n '' i; and respectively .

The

may be different each other.

Another aspect of this embodiment is described below. The state data in the state data processor 21 may be described by quantum dynamics. In this arrangement, each unit of the state data processor 21, for each state data xi may hold the state data as a density matrix p ± , and the dynamics of isolated units by a quantum master equation . In the most general case, when this density matrix cannot be written as a tensor product of smaller density matrices, a single density matrix piii 2 - · . can describe the state of multiple units ii, i 2 , ... .

The state data can be encoded in three different ways :

(1) by a density matrix at the quantum level,

(2) by an analog variable at the classical level , and

(3) by a Boolean state at the logical level.

The conversion from quantum to classical description is performed by a quantum measurement . The conversion from analog to Boolean by an analog-to-digital converter . Specifically, the state data processor 21 can be implemented by using a Ising model quantum computation device such as a DOPO (Degenerate Optical Parametric Oscillator) shown in US2017/0024658Ά1.

In Fig, 4, a coherent Ising machine (CIM) based degenerate optical parametric oscillator (DOPO) according to P.L. McMahon, et al . , "A fully-programmable 100-spin coherent Ising machine with all-to-all connections", Science 354, 614 (2016) is shown.

Since the detail of the DOPO system is shown in US2017/0024658A1 , the basic structure of the DOPO will be shown here. The state data processor 21 implemented by using the DOPO system is shown in Fig.4. The state data processor 21 in this example includes a Pump Pulse Generator (PPG) 41, a Second Harmonic Generation Device ( SHG) 42, a Periodically-poled Waveguide Device (PPWG) 43, Directional Couplers 44, an AD Converter 45, a FPGA device 46, a DA Converter 47, a Modulator 48, a Ring Cavity 49.

In this system plurality of pump pulse light wave (pseudo spin pulses) are generated by the PPG 41 and the SHG 42 and are introduced into the Ring Cavity 49 via the PPWG 43 in the time-divisional manner.

Here, the plurality of the pseudo spin pulses are in correspondence with a plurality of Ising model spins in a pseudo manner and having mutually an identical oscillation frequency .

The time between the adjacent light waves T is set to the L/c/N where L is the length of the Ring Cavity 49, c is the light speed travelling through the Ring Cavity 49, and N is a natural number N>0.

A part of the light wave travelling through the Ring Cavity (a ring resonator) 49 is guided via the first Directional Coupler 44-1 into the AD Converter 45. Hereinafter, the other part of the light wave which continues to travel in the Ring Cavity 49 to the second Directional Coupler 44-2 is called as "target wave,"

The AD Converter 45 converts the strength of the light wave introduced into a digital value, and output the value into the FPGA device 46.

In other words, the first Directional Coupler 44-1 and the AD Converter 45 a tentatively measure phases and amplitudes of the plurality of pseudo spin pulses every time the plurality of pseudo spin pulses circularly propagate in the Ring Cavity 49.

The FPGA device 46 in the DOPO system may be configured as adding AD converter 45 ' s output (which represents previous state data Xi(t) ) to

calculated using outputs from a cost evaluation unit 22, an error calculation unit 23, and modulation unit 24.

The FPGA device 46 outputs the result of the addition to the DA converter 47 whose output will be used to modulate input pulse.

The Modulator 48 generates other pump pulse light wave and modulate amplitude and phase of the light wave with output of DA converter 47 which is the analog value corresponds to the output of FPGA device 46. For example, the Modulator 48 delays the phase by n/2 when

is positive and performs amplitude modulation proportional to the absolute value of

and the Modulator 48 advances the phase by n/2 when

is negative and performs amplitude modulation proportional to the absolute value of

The modulated light wave produced by the Modulator 48 is guided into the Ring Cavity 49 via the second Directional Coupler 44-2. Note that the second Directional Coupler 44-2 introduces the modulated light into the Ring

Cavity 49 at the timing of the target wave is coming to the second Directional Coupler 44-2 , so that the light waves are synthesized, and the pseudo spin pulse.

As shown in the above, in this example, the FPGA device 46 outputs the value which represents

The synthesized light wave is guided along the Ring Cavity 49, and the FPGA device 46 repeatedly outputs the value which represents the progress of the state data xi(t) So the DOPO system works as a gain-dissipative simulator 211. The output of the FPGA device 46 of this DOPO system is introduced not only into the DA Converter 47, but also into other part of the state data processor 21 such as the projection unit 212 and the like.

Since the operation of DOPO is well known, the further detail description will be omitted here.

In other aspect of the embodiment of the present invention, the data processing apparatus 1 may be constructed from a digital processor such as CPU. In this aspect, the state data processor 21, the cost evaluation unit 22, the error calculation unit 23, and the modulation unit 24 are realized as a software program which is executed on the CPU . The program may be installed in the memory device connected to the CPU, and the memory device may store data which CPU uses, the data begin such as state data, error values or the like . The aspect of this embodiment may be realized with a generic computer device which also includes a display device and an input device such as a keyboard, and the like.

In other aspect of the embodiment of the present invention, the data processing apparatus 1 may be constructed from a digital processor such as FPGA, GPU, and the like . In this aspect, the state data processor 21, the cost evaluation unit 22 , the error calculation unit 23, and the modulation unit 24 are realized as a design implementation in terms of logic gates which are obtained after a synthesis process . The aspect of this embodiment can be interfaced with a generic computer device which includes also display device and an input device such as keyboard, and the like.

In Fig . 5 shows the schematic functional structure according to an embodiment of the present invention . As shown in the Fig . 5, the data processing apparatus 1 according to one aspect of the embodiment of the present invention includes state data nodes 31 , first-order error nodes 32, and higher-order error nodes 33.

The state data nodes 31 holds state data which is denoted by selected from a Boolean value an analog value xi, and a quantum representation (density matrix)

The state data nodes are connected each other, and a value which is held in one state data node affects the values which are held in other state data nodes, via cost function V * .

Each one of the first-order error nodes 32 is connected to a corresponding state data node 31. The first-order error nodes 32 corrects the state data which is held in the corresponding state data node 31 to correct amplitude inhomogeneity of the state data.

The higher-order error nodes 33 is connected to at least one of the state data nodes 31. Some of state data nodes 31 may not connected to the higher-order error nodes 33. In other words, the connection between the high-order error nodes 33 and the state data nodes 31 is "asymmetrical . " The connection between the high-order error nodes 33 and the state data nodes 31 is defined by the problem to be solved. The higher-order error nodes 33 may change the state data which is/are held in the state data node(s) 31 connected in order to force the constraint of the problem to be solved onto the state data.

Although only some exemplary embodiments have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope.