Title:
DECISION FEEDBACK EQUALIZATION TAPS AND RELATED APPARATUSES AND METHODS
Document Type and Number:
WIPO Patent Application WO/2022/115849
Kind Code:
A3
Abstract:
Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.
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Inventors:
SONI RAVISH (IN)
Application Number:
PCT/US2021/072568
Publication Date:
July 21, 2022
Filing Date:
November 23, 2021
Export Citation:
Assignee:
MICROCHIP TECH INC (US)
International Classes:
H04L25/03
Foreign References:
| US20170373889A1 | 2017-12-28 |
Other References:
ANKUR AGRAWAL ET AL: "A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 47, no. 12, 1 December 2012 (2012-12-01), pages 3220 - 3231, XP011485410, ISSN: 0018-9200, DOI: 10.1109/JSSC.2012.2216412
SEO JAEYOUNG ET AL: "A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 28, no. 3, 17 December 2019 (2019-12-17), pages 818 - 822, XP011775065, ISSN: 1063-8210, [retrieved on 20200224], DOI: 10.1109/TVLSI.2019.2955389
SEO JAEYOUNG ET AL: "A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 28, no. 3, 17 December 2019 (2019-12-17), pages 818 - 822, XP011775065, ISSN: 1063-8210, [retrieved on 20200224], DOI: 10.1109/TVLSI.2019.2955389
Attorney, Agent or Firm:
BOOTH, Brett C. et al. (US)
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